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[LiteX] change "standard" cache layout

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#350
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stnolting 2022-07-01 10:18:33 +02:00
parent 83e04b97cc
commit a9d4b055a8
1 changed files with 2 additions and 2 deletions
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4
rtl/system_integration/neorv32_litex_core_complex.vhd
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@ -146,8 +146,8 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
pmp_nr => ( 0, 0, 0, 8 ), -- number of PMP regions (0..16)
hpm_nr => ( 0, 0, 0, 8 ), -- number of HPM counters (0..29)
icache_en => ( false, false, true, true ), -- instruction cache enabled
icache_nb => ( 0, 0, 4, 8 ), -- number of cache blocks (lines), power of two
icache_bs => ( 0, 0, 128, 256 ), -- size of cache clock (lines) in bytes, power of two
icache_nb => ( 0, 0, 8, 8 ), -- number of cache blocks (lines), power of two
icache_bs => ( 0, 0, 64, 256 ), -- size of cache clock (lines) in bytes, power of two
icache_as => ( 1, 1, 1, 2 ), -- associativity (1 or 2)
mtime => ( false, true, true, true ) -- RISC-V machine system timers
);