mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-24 22:27:21 -04:00
Merge branch 'master' of https://github.com/stnolting/neorv32
This commit is contained in:
stnolting
commit
aa769fa210
40 changed files with 268 additions and 291 deletions
2
.github/workflows/riscv-arch-test.yml
vendored
2
.github/workflows/riscv-arch-test.yml
vendored
|
|
@ -34,4 +34,4 @@ jobs:
|
|||
backend: gcc
|
||||
|
||||
- name: '⚙️ Run RISC-V Architecture Tests'
|
||||
run: ./riscv-arch-test/run_riscv_arch_test.sh
|
||||
run: ./sim/run_riscv_arch_test.sh
|
||||
|
|
|
|||
5
.gitignore
vendored
5
.gitignore
vendored
|
|
@ -30,3 +30,8 @@ sw/image_gen/image_gen.exe
|
|||
|
||||
# example bitstreams
|
||||
/setups/examples/*.bit
|
||||
/setups/examples/*.svf
|
||||
|
||||
# riscv-arch-test
|
||||
|
||||
/sim/work/
|
||||
|
|
|
|||
2
.gitmodules
vendored
2
.gitmodules
vendored
|
|
@ -1,3 +1,3 @@
|
|||
[submodule "riscv-arch-test/work/riscv-arch-test"]
|
||||
path = riscv-arch-test/work/riscv-arch-test
|
||||
path = sw/isa-test/riscv-arch-test
|
||||
url = https://github.com/riscv/riscv-arch-test.git
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ ASM_INC ?= -I .
|
|||
# Optimization
|
||||
EFFORT ?= -Os
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
MABI ?= -mabi=ilp32
|
||||
|
|
@ -170,7 +170,7 @@ NEORV32_HOME ?= ../../..
|
|||
| _APP_INC_ | Include file folders; separated by white spaces; must be defined with `-I` prefix
|
||||
| _ASM_INC_ | Include file folders that are used only for the assembly source files (`*.S`/`*.s`).
|
||||
| _EFFORT_ | Optimization level, optimize for size (`-Os`) is default; legal values: `-O0`, `-O1`, `-O2`, `-O3`, `-Os`
|
||||
| _RISCV_TOOLCHAIN_ | The toolchain prefix to be used; follows the naming convention "architecture-vendor-output"
|
||||
| _RISCV_PREFIX_ | The toolchain prefix to be used; follows the naming convention "architecture-vendor-output-"
|
||||
| _MARCH_ | The targetd RISC-V architecture/ISA. Only `rv32` is supported by the NEORV32. Enable compiler support of optional CPU extension by adding the according extension letter (e.g. `rv32im` for _M_ CPU extension). See https://stnolting.github.io/neorv32/ug/#_enabling_risc_v_cpu_extensions[User Guide: Enabling RISC-V CPU Extensions] for more information.
|
||||
| _MABI_ | The default 32-bit integer ABI.
|
||||
| _USER_FLAGS_ | Additional flags that will be forwarded to the compiler tools
|
||||
|
|
@ -282,7 +282,7 @@ These four regions contain everything required for the application to run:
|
|||
[cols="<1,<9"]
|
||||
[options="header",grid="rows"]
|
||||
|=======================
|
||||
| Region | Description
|
||||
| Region | Description
|
||||
| `.text` | Executable instructions generated from the start-up code and all application sources.
|
||||
| `.rodata` | Constants (like strings) from the application; also the initial data for initialized variables.
|
||||
| `.data` | This section is required for the address generation of fixed (= global) variables only.
|
||||
|
|
@ -415,7 +415,7 @@ _OPTIONAL_: The MTIME machine timer (<<_io_mtime_en>> generic is _true_) and the
|
|||
To interact with the bootloader, connect the primary UART (UART0) signals (`uart0_txd_o` and
|
||||
`uart0_rxd_o`) of the processor's top entity via a serial port (-adapter) to your computer (hardware flow control is
|
||||
not used so the according interface signals can be ignored.), configure your
|
||||
terminal program using the following settings and perform a reset of the processor.
|
||||
terminal program using the following settings and perform a reset of the processor.
|
||||
|
||||
Terminal console settings (`19200-8-N-1`):
|
||||
|
||||
|
|
|
|||
|
|
@ -13,8 +13,8 @@ There are two possibilities to get this:
|
|||
2. Download and install a prebuilt version of the toolchain; this might also done via the package manager / app store of your OS
|
||||
|
||||
[TIP]
|
||||
The default toolchain prefix for this project is **`riscv32-unknown-elf`**. Of course you can use any other RISC-V
|
||||
toolchain (like `riscv64-unknown-elf`) that is capable to emit code for a `rv32` architecture. Just change the _RISCV_TOOLCHAIN_ variable in the application
|
||||
The default toolchain prefix for this project is **`riscv32-unknown-elf-`**. Of course you can use any other RISC-V
|
||||
toolchain (like `riscv64-unknown-elf-`) that is capable to emit code for a `rv32` architecture. Just change the _RISCV_PREFIX_ variable in the application
|
||||
makefile(s) according to your needs or define this variable when invoking the makefile.
|
||||
|
||||
[IMPORTANT]
|
||||
|
|
@ -264,7 +264,7 @@ More information can be found in the datasheet section https://stnolting.github.
|
|||
:sectnums:
|
||||
== Application Program Compilation
|
||||
|
||||
This guide shows how to compile an example C-code application into a NEORV32 executable that
|
||||
This guide shows how to compile an example C-code application into a NEORV32 executable that
|
||||
can be uploaded via the bootloader or the on-chip debugger.
|
||||
|
||||
[IMPORTANT]
|
||||
|
|
@ -298,7 +298,7 @@ Memory utilization:
|
|||
3176 0 120 3296 ce0 main.elf
|
||||
Compiling ../../../sw/image_gen/image_gen
|
||||
Executable (neorv32_exe.bin) size in bytes:
|
||||
3188
|
||||
3188
|
||||
----
|
||||
|
||||
[start=5]
|
||||
|
|
@ -455,7 +455,7 @@ Using the IMEM as ROM:
|
|||
|
||||
* for this boot concept the bootloader is no longer required
|
||||
* this concept only works for the internal IMEM (but can be extended to work with external memories coupled via the processor's bus interface)
|
||||
* make sure that the memory components (like block RAM) the IMEM is mapped to support an initialization via the bitstream
|
||||
* make sure that the memory components (like block RAM) the IMEM is mapped to support an initialization via the bitstream
|
||||
|
||||
[start=1]
|
||||
. At first, make sure your processor setup actually implements the internal IMEM: the `MEM_INT_IMEM_EN` generics has to be set to `true`:
|
||||
|
|
@ -469,7 +469,7 @@ Using the IMEM as ROM:
|
|||
|
||||
[start=2]
|
||||
. For this setup we do not want the bootloader to be implemented at all. Disable implementation of the bootloader by setting the
|
||||
`INT_BOOTLOADER_EN` generic to `false`. This will also modify the processor-internal IMEM so it is initialized with the executable during synthesis.
|
||||
`INT_BOOTLOADER_EN` generic to `false`. This will also modify the processor-internal IMEM so it is initialized with the executable during synthesis.
|
||||
|
||||
.Processor top entity configuration - disable internal bootloader
|
||||
[source,vhdl]
|
||||
|
|
@ -698,7 +698,7 @@ All bootloader boot configuration support uploading new executables via the on-c
|
|||
|
||||
[WARNING]
|
||||
Note that this boot configuration does not load any executable at all! Hence,
|
||||
this boot configuration is intended to be used with the on-chip debugger only.
|
||||
this boot configuration is intended to be used with the on-chip debugger only.
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,54 +0,0 @@
|
|||
# NEORV32 RISC-V Architecture Test Framework
|
||||
|
||||
## Overview
|
||||
|
||||
This sub-project folder tests the NEORV32 Processor for RISC-V compatibility
|
||||
using the [official RISC-V architecture test suite v2+](https://github.com/riscv/riscv-arch-test).
|
||||
The core's HDL sources are *simulated* using `GHDL` to provide a virtual execution platform for the test framework.
|
||||
|
||||
The following tests are supported yet:
|
||||
|
||||
* `rv32i_m/C` - compressed instructions
|
||||
* `rv32i_m/I` - base ISA
|
||||
* `rv32i_m/M` - hardware integer multiplication and division
|
||||
* `rv32i_m/privilege` - privileged architecture
|
||||
* `rv32i_m/Zifencei` - instruction stream synchronization (for example for self-modifying code)
|
||||
|
||||
|
||||
## How To Run
|
||||
|
||||
**Requirements:**
|
||||
* RISC-V GCC toolchain (`riscv32-unknown-elf`) for test program compilation
|
||||
* GHDL for simulating the HDL sources
|
||||
|
||||
To execute all the supported test* open a terminal an run:
|
||||
|
||||
```bash
|
||||
$ sh run_riscv_arch_test.sh
|
||||
```
|
||||
|
||||
:warning: Simulating all the test cases takes quite some time.
|
||||
|
||||
:warning: If the simulation of a test does not generate any signature output at all or if the signature is truncated,
|
||||
try increasing the simulation time by modiying the `SIM_TIME` variable when calling the test makefiles in `run_riscv_arch_test.sh`.
|
||||
|
||||
|
||||
## Details
|
||||
|
||||
The [`run_riscv_arch_test.sh`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/run_riscv_arch_test.sh)
|
||||
bash script does the following:
|
||||
|
||||
* Make local copies of the NEORV32 `rtl`, `sim` and `sw` folders in `work/neorv32/` to keep the project's core files clean
|
||||
* Clone (as `git submodule`) the [riscv-arch-test repository](https://github.com/riscv/riscv-arch-test) into `work/riscv-arch-test`
|
||||
* Install (copy) the custom `neorv32` test target from `port-neorv32/framework_v2.0/riscv-target` to the
|
||||
test suite's target folder `work/riscv-arch-test/riscv-target`
|
||||
* Make a copy of the original IMEM VHDL source file of the processor (in `work/neorv32/rtl/core/neorv32_imem.vhd`)
|
||||
by the simulation-optimized file (`work/neorv32/rtl/core/neorv32_imem.ORIGINAL`); the original IMEM will be overriden
|
||||
by the device makefiles with a simulation-optimized one (`neorv32/sim/rtl_modules/neorv32_imem.vhd`); the original
|
||||
IMEM is required for certain tests that use self-modifying code
|
||||
* Run the actual tests
|
||||
|
||||
More datails regarding the actual simulation process can be found in the
|
||||
[target's `README`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md).
|
||||
For more information regarding the NEORV32 Processor see the :page_facing_up:
|
||||
[NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
# Abort if any command returns != 0
|
||||
set -e
|
||||
|
||||
# Project home folder
|
||||
homedir="$( cd "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
|
||||
homedir=$homedir/..
|
||||
|
||||
# Check GCC toolchain installation
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo "> Checking RISC-V GCC toolchain..."
|
||||
echo "--------------------------------------------------------------------------"
|
||||
riscv32-unknown-elf-gcc -v
|
||||
|
||||
# Check GHDL installation
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo "> Checking GHDL simulator..."
|
||||
echo "--------------------------------------------------------------------------"
|
||||
ghdl -v
|
||||
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo "> Checking 'riscv-arch-test' GitHub repository (submodule)..."
|
||||
echo "--------------------------------------------------------------------------"
|
||||
|
||||
git submodule update --init
|
||||
|
||||
# Copy NEORV32 files
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo "> Making local copy of NEORV32 'rtl', 'sim' & 'sw' folders..."
|
||||
echo "--------------------------------------------------------------------------"
|
||||
(cd $homedir/riscv-arch-test/work ; rm -rf neorv32 ; mkdir neorv32)
|
||||
cp -r $homedir/rtl/ $homedir/riscv-arch-test/work/neorv32/.
|
||||
cp -r $homedir/sim/ $homedir/riscv-arch-test/work/neorv32/.
|
||||
cp -r $homedir/sw/ $homedir/riscv-arch-test/work/neorv32/.
|
||||
|
||||
# Copy neorv32 target folder into test suite
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo "> Copying neorv32 test-target into riscv-arch-test framework..."
|
||||
echo "--------------------------------------------------------------------------"
|
||||
cp -rf $homedir/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32 $homedir/riscv-arch-test/work/riscv-arch-test/riscv-target/.
|
||||
|
||||
# Make a local copy of the original IMEM rtl file
|
||||
echo ""
|
||||
echo ">>> Making local backup of original IMEM rtl file (work/neorv32/rtl/core/neorv32_imem.ORIGINAL)..."
|
||||
echo ""
|
||||
cp $homedir/riscv-arch-test/work/neorv32/rtl/core/neorv32_imem.vhd $homedir/riscv-arch-test/work/neorv32/rtl/core/neorv32_imem.ORIGINAL
|
||||
|
||||
# Component installation done
|
||||
ls -al
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo "> Component installation done!"
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo ""
|
||||
|
||||
|
||||
# neorv32 home folder
|
||||
NEORV32_LOCAL_HOME=$homedir/riscv-arch-test/work/neorv32
|
||||
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo "> Starting RISC-V architecture tests..."
|
||||
echo "--------------------------------------------------------------------------"
|
||||
|
||||
# Clean up everything
|
||||
make -C $homedir/riscv-arch-test/work/riscv-arch-test NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 clean
|
||||
|
||||
|
||||
# work in progress FIXME
|
||||
echo ""
|
||||
echo "\e[1;33mWARNING! 'Zifencei' test is currently disabled (work in progress). \e[0m"
|
||||
echo ""
|
||||
|
||||
|
||||
# Run tests and check results
|
||||
make --silent -C $homedir/riscv-arch-test/work/riscv-arch-test NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=850us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=I build run verify
|
||||
make --silent -C $homedir/riscv-arch-test/work/riscv-arch-test NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=400us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=C build run verify
|
||||
make --silent -C $homedir/riscv-arch-test/work/riscv-arch-test NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=800us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=M build run verify
|
||||
make --silent -C $homedir/riscv-arch-test/work/riscv-arch-test NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=200us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=privilege build run verify
|
||||
#make --silent -C $homedir/riscv-arch-test/work/riscv-arch-test NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=200us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT build run verify
|
||||
|
||||
echo ""
|
||||
echo "RISC-V architecture tests completed successfully"
|
||||
2
riscv-arch-test/work/.gitignore
vendored
2
riscv-arch-test/work/.gitignore
vendored
|
|
@ -1,2 +0,0 @@
|
|||
neorv32
|
||||
riscv-arch-test
|
||||
2
setups/osflow/.gitignore
vendored
2
setups/osflow/.gitignore
vendored
|
|
@ -1,6 +1,8 @@
|
|||
*.asc
|
||||
*.bit
|
||||
*.cfg
|
||||
*.dfu
|
||||
*.history
|
||||
*.json
|
||||
*.svf
|
||||
*-report.txt
|
||||
|
|
|
|||
|
|
@ -1,17 +1,54 @@
|
|||
## Simulation Source Folder
|
||||
# Simulation Source Folder
|
||||
|
||||
### [`ghdl`](https://github.com/stnolting/neorv32/tree/master/sim/ghdl)
|
||||
|
||||
This folder contains a script for simulating the processor using GHDL.
|
||||
## [`neorv32_tb.simple.vhd`](neorv32_tb.simple.vhd) and [`ghdl_sim.sh`](ghdl_sim)
|
||||
|
||||
### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)
|
||||
Simple testbench for the NEORV32 Processor and script for simulation using GHDL.
|
||||
|
||||
|
||||
## [`rtl_modules`](rtl_modules)
|
||||
|
||||
This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
|
||||
|
||||
### [`neorv32_tb.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.vhd)
|
||||
|
||||
VUnit testbench for the NEORV32 Processor.
|
||||
## [`neorv32_tb.vhd`](neorv32_tb.vhd) and [`run.py`](run.py)
|
||||
|
||||
### [`neorv32_tb.simple.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.simple.vhd)
|
||||
VUnit testbench and run script for the NEORV32 Processor.
|
||||
|
||||
Simple testbench for the NEORV32 Processor.
|
||||
|
||||
## [`run_riscv_arch_test.sh`](run_riscv_arch_test.sh): NEORV32 RISC-V Architecture Test Framework
|
||||
|
||||
This script tests the NEORV32 Processor for RISC-V compatibility using the
|
||||
[official RISC-V architecture test suite v2+](https://github.com/riscv/riscv-arch-test).
|
||||
The core's HDL sources are *simulated* using `GHDL` to provide a virtual execution platform for the test framework:
|
||||
|
||||
* `rv32i_m/C` - compressed instructions
|
||||
* `rv32i_m/I` - base ISA
|
||||
* `rv32i_m/M` - hardware integer multiplication and division
|
||||
* `rv32i_m/privilege` - privileged architecture
|
||||
* `rv32i_m/Zifencei` - instruction stream synchronization (for example for self-modifying code)
|
||||
|
||||
:warning: The RISC-V GCC toolchain (`riscv{32|64}-unknown-elf`) is required for program compilation, and the tests
|
||||
depend on `ghdl_sim.sh`.
|
||||
|
||||
To execute all the supported tests open a terminal and run [`./sim/run_riscv_arch_test.sh`](run_riscv_arch_test.sh),
|
||||
which does the following:
|
||||
|
||||
* Make local copies of the NEORV32 `rtl`, `sim` and `sw` folders in `work/`, to keep the project's core files clean.
|
||||
* Clone (as `git submodule`) the [riscv-arch-test repository](https://github.com/riscv/riscv-arch-test) into `sw/isa-test/riscv-arch-test`.
|
||||
* Install (copy) the custom `neorv32` test target from `sw/isa-test/port-neorv32` to the
|
||||
test suite's target folder `work/riscv-arch-test/riscv-target/neorv32`
|
||||
* Make a copy of the original IMEM VHDL source file of the processor (`cp work/neorv32/rtl/core/neorv32_imem.vhd work/neorv32/rtl/core/neorv32_imem.ORIGINAL`);
|
||||
since the IMEM will be overriden by the device makefiles with a simulation-optimized one (`neorv32/sim/rtl_modules/neorv32_imem.vhd`).
|
||||
Still, the original IMEM is required for certain tests that use self-modifying code.
|
||||
* Run the actual tests.
|
||||
|
||||
:warning: Simulating all the test cases takes quite some time.
|
||||
|
||||
:warning: If the simulation of a test does not generate any signature output at all or if the signature is truncated,
|
||||
try increasing the simulation time by modiying the `SIM_TIME` variable when calling the test makefiles in `run_riscv_arch_test.sh`.
|
||||
|
||||
More datails regarding the actual simulation process can be found in the
|
||||
[target's `README`](../sw/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md).
|
||||
For more information regarding the NEORV32 Processor see the :page_facing_up:
|
||||
[NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
||||
|
|
|
|||
|
|
@ -8,42 +8,26 @@
|
|||
# Abort if any command returns != 0
|
||||
set -e
|
||||
|
||||
cd $(dirname "$0")/..
|
||||
cd $(dirname "$0")
|
||||
|
||||
# Default simulation configuration
|
||||
# Simulation configuration
|
||||
SIM_CONFIG=--stop-time=10ms
|
||||
|
||||
# Show GHDL version
|
||||
ghdl -v
|
||||
|
||||
# Simulation time define by user?
|
||||
echo ""
|
||||
if [ -z $1 ]
|
||||
then
|
||||
echo "Using default simulation config: $SIM_CONFIG"
|
||||
else
|
||||
SIM_CONFIG=$1;
|
||||
echo "Using user simulation config: $SIM_CONFIG";
|
||||
if [ -n "$1" ]; then
|
||||
SIM_CONFIG="$1";
|
||||
fi
|
||||
echo ""
|
||||
echo "Using simulation config: $SIM_CONFIG";
|
||||
|
||||
# List files
|
||||
#echo "Simulation source files:"
|
||||
#ls -l rtl/core
|
||||
#ls -l sim
|
||||
#ls -l rtl/templates
|
||||
#echo ""
|
||||
|
||||
# Just a hint
|
||||
echo "Tip: Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to auto-enable UART[0/1]'s simulation mode (redirect UART output to simulator console)."
|
||||
echo ""
|
||||
|
||||
mkdir -p build
|
||||
|
||||
# Analyse sources; libs and images at first!
|
||||
ghdl -i --work=neorv32 rtl/core/*.vhd
|
||||
ghdl -i --work=neorv32 rtl/templates/processor/*.vhd
|
||||
ghdl -i --work=neorv32 rtl/templates/system/*.vhd
|
||||
ghdl -i --work=neorv32 sim/neorv32_tb.simple.vhd
|
||||
ghdl -i --work=neorv32 sim/uart_rx.simple.vhd
|
||||
ghdl -i --work=neorv32 --workdir=build \
|
||||
../rtl/core/*.vhd \
|
||||
../rtl/templates/processor/*.vhd \
|
||||
../rtl/templates/system/*.vhd \
|
||||
neorv32_tb.simple.vhd \
|
||||
uart_rx.simple.vhd
|
||||
|
||||
# Prepare simulation output files for UART0 and UART 1
|
||||
# - Testbench receiver log file (neorv32.testbench_uart?.out)
|
||||
|
|
@ -60,7 +44,9 @@ for item in \
|
|||
done
|
||||
|
||||
# Run simulation
|
||||
ghdl -m --work=neorv32 neorv32_tb_simple
|
||||
ghdl -r --work=neorv32 neorv32_tb_simple --max-stack-alloc=0 --ieee-asserts=disable --assert-level=error $SIM_CONFIG
|
||||
ghdl -m --work=neorv32 --workdir=build neorv32_tb_simple
|
||||
ghdl -r --work=neorv32 --workdir=build neorv32_tb_simple --max-stack-alloc=0 --ieee-asserts=disable --assert-level=error $SIM_CONFIG
|
||||
|
||||
cat neorv32.uart0.sim_mode.text.out | grep "CPU TEST COMPLETED SUCCESSFULLY!"
|
||||
|
||||
rm -rf *.{o,cf,lst,out} build
|
||||
|
|
|
|||
63
sim/run_riscv_arch_test.sh
Executable file
63
sim/run_riscv_arch_test.sh
Executable file
|
|
@ -0,0 +1,63 @@
|
|||
#!/usr/bin/env bash
|
||||
|
||||
# Abort if any command returns != 0
|
||||
set -e
|
||||
|
||||
cd $(dirname "$0")
|
||||
|
||||
header() {
|
||||
echo "--------------------------------------------------------------------------"
|
||||
echo "> $@..."
|
||||
echo "--------------------------------------------------------------------------"
|
||||
}
|
||||
|
||||
RISCV_PREFIX="${RISCV_PREFIX:-riscv32-unknown-elf-}"
|
||||
|
||||
header "Checking RISC-V GCC toolchain"
|
||||
"$RISCV_PREFIX"gcc -v
|
||||
|
||||
header "Checking 'riscv-arch-test' GitHub repository (submodule)"
|
||||
git submodule update --init
|
||||
|
||||
header "Copying neorv32 test-target into riscv-arch-test framework"
|
||||
(
|
||||
cd ../sw/isa-test
|
||||
target_device='riscv-arch-test/riscv-target/neorv32'
|
||||
if [ -d "$target_device" ]; then rm -rf "$target_device"; fi
|
||||
cp -vr port-neorv32 "$target_device"
|
||||
)
|
||||
|
||||
header "Making local copy of NEORV32 'rtl', 'sim' & 'sw' folders"
|
||||
rm -rf work
|
||||
mkdir -p work/sim
|
||||
for item in 'rtl' 'sw'; do
|
||||
cp -r ../"$item" work
|
||||
done
|
||||
for item in *.simple.vhd ghdl_sim.sh; do
|
||||
cp -r "$item" work/sim
|
||||
done
|
||||
|
||||
header "Making local backup of original IMEM rtl file (work/rtl/core/neorv32_imem.ORIGINAL)"
|
||||
(
|
||||
cd work/rtl/core/
|
||||
cp neorv32_imem.vhd neorv32_imem.ORIGINAL
|
||||
)
|
||||
|
||||
header "Starting RISC-V architecture tests"
|
||||
|
||||
makeArgs="-C ../sw/isa-test/riscv-arch-test NEORV32_LOCAL_COPY=$(pwd)/work XLEN=32 RISCV_TARGET=neorv32"
|
||||
|
||||
make $makeArgs clean
|
||||
|
||||
# work in progress FIXME
|
||||
printf "\n\e[1;33mWARNING! 'Zifencei' test is currently disabled (work in progress). \e[0m\n\n"
|
||||
|
||||
# Run tests and check results
|
||||
makeTargets='build run verify'
|
||||
make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I $makeTargets
|
||||
make --silent $makeArgs SIM_TIME=400us RISCV_DEVICE=C $makeTargets
|
||||
make --silent $makeArgs SIM_TIME=800us RISCV_DEVICE=M $makeTargets
|
||||
make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=privilege $makeTargets
|
||||
#make $makeArgs SIM_TIME=200us RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT $makeTargets
|
||||
|
||||
printf "\nRISC-V architecture tests completed successfully"
|
||||
46
sw/README.md
46
sw/README.md
|
|
@ -1,27 +1,49 @@
|
|||
## NEORV32 Software Framework
|
||||
# NEORV32 Software Framework
|
||||
|
||||
This folder provides the core of the NEORV32 software framework. This is a short description of the main folders.
|
||||
This folder provides the core of the NEORV32 software framework.
|
||||
This is a short description of the main folders.
|
||||
|
||||
### [`bootloader`](https://github.com/stnolting/neorv32/tree/master/sw/bootloader)
|
||||
|
||||
Source(s) of the default NEORV32 bootloader. A pre-built image is already installed into the rtl design via the
|
||||
`rtl/core/neorv32_bootloader_image.vhd` file.
|
||||
## [`bootloader`](bootloader)
|
||||
|
||||
### [`common`](https://github.com/stnolting/neorv32/tree/master/sw/common)
|
||||
Source(s) of the default NEORV32 bootloader.
|
||||
A pre-built image is already installed into the rtl design via the `rtl/core/neorv32_bootloader_image.vhd` file.
|
||||
|
||||
|
||||
## [`common`](common)
|
||||
|
||||
NEORV32-specific common files for all bootloader and application programs: linker script for executable generation and
|
||||
processor start-up code.
|
||||
|
||||
### [`example`](https://github.com/stnolting/neorv32/tree/master/sw/example)
|
||||
|
||||
## [`example`](example)
|
||||
|
||||
Several example programs for testing and for getting started.
|
||||
|
||||
### [`image_gen`](https://github.com/stnolting/neorv32/tree/master/sw/image_gen)
|
||||
|
||||
This folder contains a simple program that is used to create NEORV32 executables (for upload via bootloader) and VHDL memory
|
||||
initializiation files (for memory-persistent applications and for the bootloader). This program is automatically compiled using
|
||||
the native GCC when invoking one of the application compilation makefiles.
|
||||
## [`image_gen`](image_gen)
|
||||
|
||||
### [`lib`](https://github.com/stnolting/neorv32/tree/master/sw/lib)
|
||||
This folder contains a simple program that is used to create NEORV32 executables (for upload via bootloader) and VHDL
|
||||
memory initializiation files (for memory-persistent applications and for the bootloader).
|
||||
This program is automatically compiled using the native GCC when invoking one of the application compilation makefiles.
|
||||
|
||||
|
||||
## [`lib`](lib)
|
||||
|
||||
Core libraries (sources and header files) and helper functions for using the processor peripherals and the CPU itself.
|
||||
|
||||
|
||||
## [`ocd-firmware`](ocd-firmware)
|
||||
|
||||
*TBC*
|
||||
|
||||
|
||||
## [`openocd`](openocd)
|
||||
|
||||
*TBC*
|
||||
|
||||
|
||||
## [`isa-test`](isa-test)
|
||||
|
||||
NEORV32 RISC-V Architecture Test Framework.
|
||||
See [sim/README](../sim/README.md).
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -185,10 +185,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH ?= -march=rv32i
|
||||
|
|
@ -112,10 +112,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ RUN_TARGET=\
|
|||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "copying/using SIM-only IMEM (ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/rtl_modules/neorv32_imem.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
|
|
@ -33,7 +33,7 @@ RUN_TARGET=\
|
|||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
sh $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
|
||||
cp $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
|
@ -14,7 +14,7 @@ RUN_TARGET=\
|
|||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "copying/using SIM-only IMEM (ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/rtl_modules/neorv32_imem.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
|
|
@ -33,7 +33,7 @@ RUN_TARGET=\
|
|||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
sh $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
|
||||
cp $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
|
@ -14,7 +14,7 @@ RUN_TARGET=\
|
|||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "copying/using SIM-only IMEM (ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/rtl_modules/neorv32_imem.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
|
|
@ -33,7 +33,7 @@ RUN_TARGET=\
|
|||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
sh $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
|
||||
cp $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
|
@ -33,7 +33,7 @@ RUN_TARGET=\
|
|||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
sh $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
|
||||
cp $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
|
@ -14,7 +14,7 @@ RUN_TARGET=\
|
|||
rm -f $(NEORV32_LOCAL_COPY)/*.out; \
|
||||
echo "copying/using SIM-only IMEM (ROM!)"; \
|
||||
rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/rtl_modules/neorv32_imem.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
cp -f $(NEORV32_LOCAL_COPY)/sim/neorv32_imem.simple.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-ARCH-TEST TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.simple.vhd; \
|
||||
|
|
@ -33,7 +33,7 @@ RUN_TARGET=\
|
|||
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
|
||||
touch $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out; \
|
||||
sh $(NEORV32_LOCAL_COPY)/sim/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
|
||||
cp $(NEORV32_LOCAL_COPY)/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
cp $(NEORV32_LOCAL_COPY)/sim/neorv32.uart0.sim_mode.data.out $(*).signature.output;
|
||||
|
||||
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
|
@ -52,7 +52,7 @@ ASM_INC ?= -I .
|
|||
EFFORT ?= -Os
|
||||
|
||||
# Compiler toolchain
|
||||
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
|
||||
RISCV_PREFIX ?= riscv32-unknown-elf-
|
||||
|
||||
# CPU architecture and ABI
|
||||
MARCH = -march=rv32i
|
||||
|
|
@ -105,10 +105,10 @@ OBJ = $(SRC:%=%.o)
|
|||
# Tools and flags
|
||||
# -----------------------------------------------------------------------------
|
||||
# Compiler tools
|
||||
CC = $(RISCV_TOOLCHAIN)-gcc
|
||||
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
|
||||
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
|
||||
SIZE = $(RISCV_TOOLCHAIN)-size
|
||||
CC = $(RISCV_PREFIX)gcc
|
||||
OBJDUMP = $(RISCV_PREFIX)objdump
|
||||
OBJCOPY = $(RISCV_PREFIX)objcopy
|
||||
SIZE = $(RISCV_PREFIX)size
|
||||
|
||||
# Host native compiler
|
||||
CC_X86 = g++ -Wall -O -g
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue