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Merge branch 'main' into sw_cleanup
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stnolting
commit
ab6bca3bb4
7 changed files with 133 additions and 30 deletions
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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| Date | Version | Comment | Ticket |
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|:----:|:-------:|:--------|:------:|
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| 12.04.2025 | 1.11.2.7 | :sparkles: add PWM polarity configuration | [#1230](https://github.com/stnolting/neorv32/pull/1230) |
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| 07.04.2025 | 1.11.2.6 | :bug: fix SDI input synchronization | [#1227](https://github.com/stnolting/neorv32/pull/1227) |
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| 05.04.2025 | 1.11.2.5 | minor rtl edits and optimizations | [#1225](https://github.com/stnolting/neorv32/pull/1225) |
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| 01.04.2025 | 1.11.2.4 | :bug: fix bug in PWM clock prescaler | [#1222](https://github.com/stnolting/neorv32/pull/1222) |
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@ -30,13 +30,14 @@ Depending on the configured number channels, the PWM module provides 16 configur
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be accessed without raising an exception. However, registers above `IO_PWM_NUM_CH-1` are read-only and hardwired to
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all-zero.
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Each configuration provides a 1-bit enable flag to enable/disable the according channel, an 8-bit register for setting
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the duty cycle and a 3-bit clock prescaler select as well as a 10-bit clock diver for _coarse_ and _fine_ tuning of the
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carrier frequency, respectively.
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Each configuration provides a 1-bit enable flag to enable/disable the according channel, a 1-bit flag for setting the
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channel polarity, an 8-bit register for setting the duty cycle and a 3-bit clock prescaler select as well as a 10-bit clock
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diver for _coarse_ and _fine_ tuning of the carrier frequency, respectively.
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A channel is enabled by setting the `PWM_CFG_EN` bit. If this bit is cleared the according PWM output is set to zero.
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The duty cycle is programmed via the 8 `PWM_CFG_DUTY` bits. Based on the value programmed to this bits the duty cycle
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the resulting duty cycle of the according channel can be computed by the following formula:
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A channel is enabled by setting the `PWM_CFG_EN` bit. If this bit is cleared the according PWM output is deasserted
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(zero if channel polarity is not inverted, one if inverted). The duty cycle is programmed via the 8 `PWM_CFG_DUTY` bits.
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Based on the value programmed to these bits the resulting duty cycle of the according channel can be computed by the
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following formula:
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_Duty Cycle_[%] = `PWM_CFG_DUTY` / 2^8^
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@ -66,13 +67,15 @@ _f~PWM~_[Hz] = _f~main~_[Hz] / (2^8^ * `clock_prescaler` * (1 + `PWM_CFG_CDIV`))
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.5+<| `0xfff00000` .5+<| `CHANNEL_CFG[0]` <|`31` - `PWM_CFG_EN` ^| r/w <| Channel 0: channel enabled when set
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<|`30:28` - `PWM_CFG_PRSC_MSB:PWM_CFG_PRSC_LSB` ^| r/w <| Channel 0: 3-bit clock prescaler select
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<|`27:18` ^| r/- <| Channel 0: _reserved_, hardwired to zero
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<|`27` - `PWM_CFG_POL` ^| r/w <| Channel 0: channel polarity, inverted when set
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<|`26:18` ^| r/- <| Channel 0: _reserved_, hardwired to zero
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<|`17:8` - `PWM_CFG_CDIV_MSB:PWM_CFG_CDIV_LSB` ^| r/w <| Channel 0: 10-bit clock divider
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<|`7:0` - `PWM_CFG_DUTY_MSB:PWM_CFG_DUTY_LSB` ^| r/w <| Channel 0: 8-bit duty cycle
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| `0xfff00004` ... `0xfff00038` | `CHANNEL_CFG[1]` ... `CHANNEL_CFG[14]` | ... | r/w <| Channels 1 to 14
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.5+<| `0xfff0003C` .5+<| `CHANNEL_CFG[15]` <|`31` - `PWM_CFG_EN` ^| r/w <| Channel 15: channel enabled when set
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<|`30:28` - `PWM_CFG_PRSC_MSB:PWM_CFG_PRSC_LSB` ^| r/w <| Channel 15: 3-bit clock prescaler select
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<|`27:18` ^| r/- <| Channel 15: _reserved_, hardwired to zero
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<|`27` - `PWM_CFG_POL` ^| r/w <| Channel 15: channel polarity, inverted when set
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<|`26:18` ^| r/- <| Channel 15: _reserved_, hardwired to zero
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<|`17:8` - `PWM_CFG_CDIV_MSB:PWM_CFG_CDIV_LSB` ^| r/w <| Channel 15: 10-bit clock divider
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<|`7:0` - `PWM_CFG_DUTY_MSB:PWM_CFG_DUTY_LSB` ^| r/w <| Channel 15: 8-bit duty cycle
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|=======================
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@ -29,7 +29,7 @@ package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110206"; -- hardware version
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110207"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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constant XLEN : natural := 32; -- native data path width
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@ -158,6 +158,7 @@ architecture neorv32_pwm_channel_rtl of neorv32_pwm_channel is
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-- configuration register --
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signal cfg_en : std_ulogic; -- channel enable
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signal cfg_prsc : std_ulogic_vector(2 downto 0); -- (course) clock prescaler select
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signal cfg_pol : std_ulogic; -- channel polarity
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signal cfg_cdiv : std_ulogic_vector(9 downto 0); -- (fine) clock divider
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signal cfg_duty : std_ulogic_vector(7 downto 0); -- duty cycle
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@ -175,12 +176,14 @@ begin
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if (rstn_i = '0') then
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cfg_en <= '0';
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cfg_prsc <= (others => '0');
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cfg_pol <= '0';
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cfg_cdiv <= (others => '0');
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cfg_duty <= (others => '0');
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elsif rising_edge(clk_i) then
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if (we_i = '1') then
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cfg_en <= wdata_i(31);
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cfg_prsc <= wdata_i(30 downto 28);
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cfg_pol <= wdata_i(27);
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cfg_cdiv <= wdata_i(17 downto 8);
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cfg_duty <= wdata_i(7 downto 0);
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end if;
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@ -188,7 +191,7 @@ begin
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end process config_write;
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-- read access --
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rdata_o <= cfg_en & cfg_prsc & "0000000000" & cfg_cdiv & cfg_duty when (re_i = '1') else (others => '0');
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rdata_o <= cfg_en & cfg_prsc & cfg_pol & "000000000" & cfg_cdiv & cfg_duty when (re_i = '1') else (others => '0');
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-- enable global clock generator --
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clkgen_en_o <= cfg_en;
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@ -226,9 +229,9 @@ begin
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-- pwm output --
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if (cfg_en = '0') or (unsigned(cnt_duty) >= unsigned(cfg_duty)) then
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pwm_o <= '0';
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pwm_o <= cfg_pol; -- deasserted
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else
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pwm_o <= '1';
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pwm_o <= not cfg_pol; -- asserted
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end if;
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end if;
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@ -14,6 +14,7 @@
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#ifndef NEORV32_PWM_H
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#define NEORV32_PWM_H
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#include <stdbool.h>
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#include <stdint.h>
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@ -36,6 +37,7 @@ enum CHANNEL_CFG_enum {
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PWM_CFG_CDIV_LSB = 8, /**< PWM configuration register(8) (r/w): Clock divider (10-bit), LSB */
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PWM_CFG_CDIV_MSB = 17, /**< PWM configuration register(17) (r/w): Clock divider (10-bit), MSB */
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PWM_CFG_POL = 27, /**< PWM configuration register(27) (r/w): Channel polarity, inverted when set */
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PWM_CFG_PRSC_LSB = 28, /**< PWM configuration register(28) (r/w): Clock prescaler select (3-bit), LSB */
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PWM_CFG_PRSC_MSB = 30, /**< PWM configuration register(30) (r/w): Clock prescaler select (3-bit), MSB */
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PWM_CFG_EN = 31 /**< PWM configuration register(31) (r/w): channel enable */
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@ -51,6 +53,7 @@ int neorv32_pwm_available(void);
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int neorv32_pmw_get_num_channels(void);
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void neorv32_pwm_ch_enable(int channel);
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void neorv32_pwm_ch_disable(int channel);
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void neorv32_pwm_ch_set_polarity(int channel, bool inverted);
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void neorv32_pwm_ch_set_clock(int channel, int prsc, int cdiv);
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void neorv32_pwm_ch_set_duty(int channel, int duty);
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/**@}*/
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@ -80,6 +80,24 @@ void neorv32_pwm_ch_disable(int channel) {
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}
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/**********************************************************************//**
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* Set PWM channel's polarity configuration.
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*
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* @param[in] channel Channel select (0..15).
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* @param[in] normal polarity if false (default), inverted polarity if true
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**************************************************************************/
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void neorv32_pwm_ch_set_polarity(int channel, bool inverted) {
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channel &= 0xf; // constrain range
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if (inverted) {
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NEORV32_PWM->CHANNEL_CFG[channel] |= ((uint32_t)(1 << PWM_CFG_POL));
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} else {
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NEORV32_PWM->CHANNEL_CFG[channel] &= ~((uint32_t)(1 << PWM_CFG_POL));
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}
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}
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/**********************************************************************//**
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* Set PWM channel's clock configuration.
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*
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@ -92,7 +110,7 @@ void neorv32_pwm_ch_set_clock(int channel, int prsc, int cdiv) {
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channel &= 0xf; // constrain range
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uint32_t tmp = NEORV32_PWM->CHANNEL_CFG[channel];
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tmp &= 0x800000ffU; // clear current prsc and cdiv, keep enable and duty
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tmp &= 0x880000ffU; // clear current prsc and cdiv, keep enable, polarity, and duty
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tmp |= ((uint32_t)(prsc & 0x7U)) << PWM_CFG_PRSC_LSB;
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tmp |= ((uint32_t)(cdiv & 0x3ffU)) << PWM_CFG_CDIV_LSB;
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NEORV32_PWM->CHANNEL_CFG[channel] = tmp;
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@ -528,43 +528,118 @@
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<size>0x40</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Control register</description>
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<name>CHANNEL_CFG[0]</name>
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<description>Channel 0 configuration register</description>
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<addressOffset>0x00</addressOffset>
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<fields>
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<field>
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<name>PWM_CTRL_EN</name>
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<bitRange>[0:0]</bitRange>
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<description>PWM controller enable flag</description>
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<name>PWM_CFG_DUTY</name>
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<bitRange>[7:0]</bitRange>
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<description>Duty cycle</description>
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</field>
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<field>
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<name>PWM_CTRL_PRSCx</name>
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<bitRange>[3:1]</bitRange>
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<name>PWM_CFG_CDIV</name>
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<bitRange>[17:8]</bitRange>
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<description>Clock divider</description>
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</field>
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<field>
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<name>PWM_CFG_POL</name>
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<bitRange>[27:27]</bitRange>
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<description>Channel polarity, inverted when set</description>
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</field>
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<field>
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<name>PWM_CFG_PRSC</name>
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<bitRange>[30:28]</bitRange>
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<description>Clock prescaler select</description>
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</field>
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<field>
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<name>PWM_CFG_EN</name>
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<bitRange>[31:31]</bitRange>
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<description>Channel enable</description>
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</field>
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</fields>
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</register>
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<register>
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<name>DC[0]</name>
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<description>Duty cycle register 0</description>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[1]</name>
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<description>Channel 1 configuration register</description>
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<addressOffset>0x04</addressOffset>
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</register>
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<register>
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<name>DC[1]</name>
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<description>Duty cycle register 1</description>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[2]</name>
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<description>Channel 2 configuration register</description>
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<addressOffset>0x08</addressOffset>
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</register>
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<register>
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<name>DC[2]</name>
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<description>Duty cycle register 2</description>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[3]</name>
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<description>Channel 3 configuration register</description>
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<addressOffset>0x0C</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[4]</name>
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<description>Channel 4 configuration register</description>
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<addressOffset>0x10</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[5]</name>
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<description>Channel 5 configuration register</description>
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<addressOffset>0x14</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[6]</name>
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<description>Channel 6 configuration register</description>
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<addressOffset>0x18</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[7]</name>
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<description>Channel 7 configuration register</description>
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<addressOffset>0x1C</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[8]</name>
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<description>Channel 8 configuration register</description>
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<addressOffset>0x20</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[9]</name>
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<description>Channel 9 configuration register</description>
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<addressOffset>0x24</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[10]</name>
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<description>Channel 10 configuration register</description>
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<addressOffset>0x28</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[11]</name>
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<description>Channel 11 configuration register</description>
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<addressOffset>0x2C</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[12]</name>
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<description>Channel 12 configuration register</description>
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<addressOffset>0x30</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[13]</name>
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<description>Channel 13 configuration register</description>
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<addressOffset>0x34</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[14]</name>
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<description>Channel 14 configuration register</description>
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<addressOffset>0x38</addressOffset>
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</register>
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<register derivedFrom="CHANNEL_CFG[0]">
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<name>CHANNEL_CFG[15]</name>
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<description>Channel 15 configuration register</description>
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<addressOffset>0x3C</addressOffset>
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</register>
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</registers>
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</peripheral>
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