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[regfile] generic renaming

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stnolting 2023-10-14 16:50:51 +02:00
parent 2eef2228a3
commit ac71c90e75
2 changed files with 3 additions and 3 deletions
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2
rtl/core/neorv32_cpu.vhd
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@ -274,7 +274,7 @@ begin
-- -------------------------------------------------------------------------------------------
neorv32_cpu_regfile_inst: entity neorv32.neorv32_cpu_regfile
generic map (
RVE => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
RVE_EN => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
RS3_EN => regfile_rs3_en_c, -- enable 3rd read port
RS4_EN => regfile_rs4_en_c -- enable 4th read port
)

4
rtl/core/neorv32_cpu_regfile.vhd
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@ -53,7 +53,7 @@ use neorv32.neorv32_package.all;
entity neorv32_cpu_regfile is
generic (
RVE : boolean; -- implement embedded RF extension?
RVE_EN : boolean; -- implement embedded RF extension?
RS3_EN : boolean; -- enable 3rd read port
RS4_EN : boolean -- enable 4th read port
);
@ -77,7 +77,7 @@ end neorv32_cpu_regfile;
architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
-- auto-configuration --
constant addr_bits_c : natural := cond_sel_natural_f(RVE, 4, 5); -- address width
constant addr_bits_c : natural := cond_sel_natural_f(RVE_EN, 4, 5); -- address width
-- register file --
type reg_file_t is array ((2**addr_bits_c)-1 downto 0) of std_ulogic_vector(XLEN-1 downto 0);