updated docs

2025-04-23 21:57:33 -04:00 · 2020-09-14 10:03:56 +02:00 · 2020-09-14 10:03:56 +02:00 · ae340b3198
commit ae340b3198
parent 8386169176
3 changed files with 53 additions and 16 deletions
--- a/README.md
+++ b/README.md
@ -152,6 +152,7 @@ Highly customizable processor configuration:
 - Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
 - Optional GARO-based true random number generator (TRNG)
 - Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
+- Optional custom functions unit (CFU) for tightly-coupled custom co-processors
 - System configuration information memory to check hardware configuration by software (SYSINFO)

 ### CPU Features
@ -201,7 +202,7 @@ the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/ma
  * CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
  * System instructions: `MRET` `WFI`
  * Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]`
-  * Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` `marchid` `mimpid` `mhartid` `mzext`(custom)
+  * Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
  * Supported exceptions and interrupts:
    * Misaligned instruction address
    * Instruction access fault
@ -254,6 +255,7 @@ Results generated for hardware version: `1.3.6.5`
 |:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
 | BOOT ROM  | Bootloader ROM (4kB)                            |   4 |   1 |      32 768 |    0 |
 | BUSSWITCH | Mux for CPU I & D interfaces                    |  62 |   8 |           0 |    0 |
+| CFU       | Custom functions unit                           |   - |   - |           - |    - |
 | DEVNULL   | Dummy device                                    |   3 |   1 |           0 |    0 |
 | DMEM      | Processor-internal data memory (8kB)            |  12 |   2 |      65 536 |    0 |
 | GPIO      | General purpose input/output ports              |  40 |  33 |           0 |    0 |
@ -475,7 +477,8 @@ entity neorv32_top is
    IO_PWM_USE                   : boolean := true;   -- implement pulse-width modulation unit (PWM)?
    IO_WDT_USE                   : boolean := true;   -- implement watch dog timer (WDT)?
    IO_TRNG_USE                  : boolean := false;  -- implement true random number generator (TRNG)?
-    IO_DEVNULL_USE               : boolean := true    -- implement dummy device (DEVNULL)?
+    IO_DEVNULL_USE               : boolean := true;   -- implement dummy device (DEVNULL)?
+    IO_CFU_USE                   : boolean := false   -- implement custom functions unit (CFU)?
  );
  port (
    -- Global control --
@ -653,10 +656,11 @@ to [open a new issue](https://github.com/stnolting/neorv32/issues) or directly [

 If you'd like to contribute:

-1. [Fork](https://github.com/stnolting/neorv32/fork) this repository
-2. Create a feature branch in your fork: `git checkout -b cool_new_feature`
-3. Commit your modifications: `git commit -am 'This is awesome because ...'`
-4. Push to the branch: `git push origin cool_new_feature`
+1. [Fork](https://github.com/stnolting/neorv32/fork) this repository and clone the fork
+2. Create a feature branch in your fork: `git checkout -b awesome_new_feature_branch`
+3. Create a new remote for the upstream repo: `git remote add https://github.com/stnolting/neorv32`
+3. Commit your modifications: `git commit -m "Awesome new feature!"`
+4. Push to the branch: `git push origin awesome_new_feature_branch`
 5. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)

 Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
--- a/docs/NEORV32.pdf
+++ b/docs/NEORV32.pdf
--- a/rtl/core/neorv32_package.vhd
+++ b/rtl/core/neorv32_package.vhd
@ -41,7 +41,7 @@ package neorv32_package is
  -- Architecture Constants/Configuration ---------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  constant data_width_c  : natural := 32; -- data width - FIXED!
-  constant hw_version_c  : std_ulogic_vector(31 downto 0) := x"01040005"; -- no touchy!
+  constant hw_version_c  : std_ulogic_vector(31 downto 0) := x"01040200"; -- no touchy!
  constant pmp_max_r_c   : natural := 8; -- max PMP regions
  constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2

@ -125,16 +125,24 @@ package neorv32_package is
  constant pwm_ctrl_addr_c      : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"00000000");
  constant pwm_duty_addr_c      : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"00000004");

-  -- True Random Number generator (TRNG) --
+  -- True Random Number Generator (TRNG) --
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
  constant trng_size_c          : natural := 1*4; -- bytes, fixed!
  constant trng_ctrl_addr_c     : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000");

  -- RESERVED --
 --constant ???_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4"; -- base address, fixed!
--constant ???_size_c           : natural := 7*4; -- bytes, fixed!
+--constant ???_size_c           : natural := 3*4; -- bytes, fixed!

-  -- System Information Memory (with SIMULATION output) (SYSINFO) --
+  -- Custom Functions Unit (CFU) --
+  constant cfu_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
+  constant cfu_size_c           : natural := 4*4; -- bytes, fixed!
+  constant cfu_reg0_addr_c      : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"00000000");
+  constant cfu_reg1_addr_c      : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"00000004");
+  constant cfu_reg2_addr_c      : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"00000008");
+  constant cfu_reg3_addr_c      : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"0000000C");
+
+  -- System Information Memory (SYSINFO) --
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
  constant sysinfo_size_c       : natural := 8*4; -- bytes, fixed!

@ -424,7 +432,8 @@ package neorv32_package is
      IO_PWM_USE                   : boolean := true;   -- implement pulse-width modulation unit (PWM)?
      IO_WDT_USE                   : boolean := true;   -- implement watch dog timer (WDT)?
      IO_TRNG_USE                  : boolean := false;  -- implement true random number generator (TRNG)?
-      IO_DEVNULL_USE               : boolean := true    -- implement dummy device (DEVNULL)?
+      IO_DEVNULL_USE               : boolean := true;   -- implement dummy device (DEVNULL)?
+      IO_CFU_USE                   : boolean := false   -- implement custom functions unit (CFU)?
    );
    port (
      -- Global control --
@ -1046,8 +1055,8 @@ package neorv32_package is
    );
  end component;

-  ---- Component: Dummy Device with SIM Output (DEVNULL) -------------------------------------
-  ---- -------------------------------------------------------------------------------------------
+  -- Component: Dummy Device with SIM Output (DEVNULL) --------------------------------------
+  -- -------------------------------------------------------------------------------------------
  component neorv32_devnull
    port (
      -- host access --
@ -1061,8 +1070,31 @@ package neorv32_package is
    );
  end component;

-  ---- Component: System Configuration Information Memory (SYSINFO) ---------------------------
-  ---- -------------------------------------------------------------------------------------------
+  -- Component: Custom Functions Unit (CFU) -------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  component neorv32_cfu
+    port (
+      -- host access --
+      clk_i       : in  std_ulogic; -- global clock line
+      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
+      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
+      rden_i      : in  std_ulogic; -- read enable
+      wren_i      : in  std_ulogic; -- write enable
+      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
+      data_o      : out std_ulogic_vector(31 downto 0); -- data out
+      ack_o       : out std_ulogic; -- transfer acknowledge
+      -- clock generator --
+      clkgen_en_o : out std_ulogic; -- enable clock generator
+      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
+      -- interrupt --
+      irq_o       : out std_ulogic
+      -- custom io --
+      -- ...
+    );
+  end component;
+
+  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
+  -- -------------------------------------------------------------------------------------------
  component neorv32_sysinfo
    generic (
      -- General --
@ -1091,7 +1123,8 @@ package neorv32_package is
      IO_PWM_USE        : boolean := true;   -- implement pulse-width modulation unit (PWM)?
      IO_WDT_USE        : boolean := true;   -- implement watch dog timer (WDT)?
      IO_TRNG_USE       : boolean := true;   -- implement true random number generator (TRNG)?
-      IO_DEVNULL_USE    : boolean := true    -- implement dummy device (DEVNULL)?
+      IO_DEVNULL_USE    : boolean := true;   -- implement dummy device (DEVNULL)?
+      IO_CFU_USE        : boolean := true    -- implement custom functions unit (CFU)?
    );
    port (
      -- host access --