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[docs] remove privileged IO access PMA

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stnolting 2024-12-27 15:09:46 +01:00
parent bd57c252cb
commit aeec5239c1
20 changed files with 20 additions and 20 deletions
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2
docs/datasheet/soc_bootrom.adoc
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@ -11,7 +11,7 @@
| Top entity ports: | none |
| Configuration generics: | `BOOT_MODE_SELECT` | implement BOOTROM when `BOOT_MODE_SELECT` = 0; see <<_boot_configuration>>
| CPU interrupts: | none |
| Access restrictions: 2+| privileged access only, read-only
| Access restrictions: 2+| read-only
|=======================

2
docs/datasheet/soc_cfs.adoc
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@ -15,7 +15,7 @@
| | `IO_CFS_IN_SIZE` | size of `cfs_in_i`
| | `IO_CFS_OUT_SIZE` | size of `cfs_out_o`
| CPU interrupts: | fast IRQ channel 1 | CFS interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_crc.adoc
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@ -11,7 +11,7 @@
| Top entity ports: | none |
| Configuration generics: | `IO_CRC_EN` | implement CRC module when `true`
| CPU interrupts: | none |
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_dma.adoc
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@ -11,7 +11,7 @@
| Top entity ports: | none |
| Configuration generics: | `IO_DMA_EN` | implement DMA when `true`
| CPU interrupts: | fast IRQ channel 10 | DMA transfer done (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_gpio.adoc
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@ -12,7 +12,7 @@
| | `gpio_i` | 64-bit parallel input port
| Configuration generics: | `IO_GPIO_NUM` | number of input/output pairs to implement (0..64)
| CPU interrupts: | none |
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_gptmr.adoc
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@ -11,7 +11,7 @@
| Top entity ports: | none |
| Configuration generics: | `IO_GPTMR_EN` | implement general purpose timer when `true`
| CPU interrupts: | fast IRQ channel 12 | timer interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_neoled.adoc
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@ -12,7 +12,7 @@
| Configuration generics: | `IO_NEOLED_EN` | implement NEOLED controller when `true`
| | `IO_NEOLED_TX_FIFO` | TX FIFO depth, has to be a power of 2, min 1
| CPU interrupts: | fast IRQ channel 9 | configurable NEOLED data FIFO interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_onewire.adoc
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@ -13,7 +13,7 @@
| Configuration generics: | `IO_ONEWIRE_EN` | implement ONEWIRE interface controller when `true`
| | `IO_ONEWIRE_FIFO` | RTX fifo depth, has to be zero or a power of two, min 1
| CPU interrupts: | fast IRQ channel 13 | operation done interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_pwm.adoc
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@ -11,7 +11,7 @@
| Top entity ports: | `pwm_o` | PWM output channels (16-bit)
| Configuration generics: | `IO_PWM_NUM_CH` | number of PWM channels to implement (0..16)
| CPU interrupts: | none |
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_sdi.adoc
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@ -15,7 +15,7 @@
| Configuration generics: | `IO_SDI_EN` | implement SDI controller when `true`
| | `IO_SDI_FIFO` | data FIFO size, has to a power of two, min 1
| CPU interrupts: | fast IRQ channel 11 | configurable SDI interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_slink.adoc
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@ -23,7 +23,7 @@
| | `IO_SLINK_TX_FIFO` | TX FIFO depth (1..32k), has to be a power of two, min 1
| CPU interrupts: | fast IRQ channel 14 | RX SLINK IRQ (see <<_processor_interrupts>>)
| | fast IRQ channel 15 | TX SLINK IRQ (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_spi.adoc
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@ -15,7 +15,7 @@
| Configuration generics: | `IO_SPI_EN` | implement SPI controller when `true`
| | `IO_SPI_FIFO` | FIFO depth, has to be a power of two, min 1
| CPU interrupts: | fast IRQ channel 6 | configurable SPI interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_sysinfo.adoc
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@ -10,7 +10,7 @@
| Top entity ports: | none |
| Configuration generics: | * | most of the top's configuration generics
| CPU interrupts: | none |
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_trng.adoc
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@ -12,7 +12,7 @@
| Configuration generics: | `IO_TRNG_EN` | implement TRNG when `true`
| | `IO_TRNG_FIFO` | data FIFO depth, min 1, has to be a power of two
| CPU interrupts: | none
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_twd.adoc
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@ -15,7 +15,7 @@
| Configuration generics: | `IO_TWD_EN` | implement TWD controller when `true`
| | `IO_TWD_FIFO` | RX/TX FIFO depth, has to be a power of two, min 1
| CPU interrupts: | fast IRQ channel 0 | FIFO status interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_twi.adoc
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@ -15,7 +15,7 @@
| Configuration generics: | `IO_TWI_EN` | implement TWI controller when `true`
| | `IO_TWI_FIFO` | FIFO depth, has to be a power of two, min 1
| CPU interrupts: | fast IRQ channel 7 | FIFO empty and module idle interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_uart.adoc
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@ -17,7 +17,7 @@
| | `UART0_TX_FIFO` | TX FIFO depth (power of 2, min 1)
| CPU interrupts: | fast IRQ channel 2 | RX interrupt
| | fast IRQ channel 3 | TX interrupt (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_wdt.adoc
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@ -11,7 +11,7 @@
| Top entity ports: | none |
| Configuration generics: | `IO_WDT_EN` | implement watchdog when `true`
| CPU interrupts: | none |
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================

2
docs/datasheet/soc_xip.adoc
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@ -18,7 +18,7 @@
| | `XIP_CACHE_NUM_BLOCKS` | number of blocks in XIP cache; has to be a power of two
| | `XIP_CACHE_BLOCK_SIZE` | number of bytes per XIP cache block; has to be a power of two, min 4
| CPU interrupts: | none |
| Access restrictions: 2+| control registers: privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| control registers: non-32-bit write accesses are ignored
| 2+| XIP data access: read-only
|=======================

2
docs/datasheet/soc_xirq.adoc
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@ -11,7 +11,7 @@
| Top entity ports: | `xirq_i` | External interrupts input (32-bit)
| Configuration generics: | `XIRQ_NUM_CH` | Number of external IRQ channels to implement (0..32)
| CPU interrupts: | fast IRQ channel 8 | XIRQ (see <<_processor_interrupts>>)
| Access restrictions: 2+| privileged access only, non-32-bit write accesses are ignored
| Access restrictions: 2+| non-32-bit write accesses are ignored
|=======================