mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-23 13:47:33 -04:00
added 'show hardware config' function to RTE; removed mscratch as return address buffer in crt0.S
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stnolting
parent
4b8d109388
commit
b0d72b8e37
3 changed files with 184 additions and 13 deletions
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@ -1,7 +1,7 @@
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/* ################################################################################################# */
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/* # << NEORV32 - crt0.S - Application Start-Up Code >> # */
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/* # << NEORV32 - crt0.S - Application Start-Up Code & Minimal Runtime Environment >> # */
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/* # ********************************************************************************************* # */
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/* # The start-up code provides a minimal runtime environment that catches all exceptions/ # */
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/* # The start-up code provides a minimal runtime environment that catches all exceptions and # */
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/* # interrupts and delegates them to the handler functions (installed by user via dedicated # */
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/* # install function from the neorv32 runtime environment library). # */
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/* # ********************************************************************************************* # */
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@ -320,7 +320,6 @@ __crt0_neorv32_rte_execute:
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// push ra
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addi sp, sp, -4
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sw ra, 0(sp)
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csrrw zero, mscratch, ra
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jalr ra, t0 // call second-level handler
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@ -44,7 +44,8 @@
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// prototypes
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void neorv32_rte_enable_debug_mode(void);
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int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void));
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int neorv32_rte_exception_uninstall(uint8_t exc_id);
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int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void));
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int neorv32_rte_exception_uninstall(uint8_t exc_id);
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void neorv32_rte_print_hw_config(void);
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#endif // neorv32_rte_h
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@ -43,8 +43,10 @@
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#include "neorv32_rte.h"
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// Privates
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static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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static void __neorv32_rte_print_hw_version(void) __attribute__((unused));
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/**********************************************************************//**
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@ -151,19 +153,27 @@ static void __neorv32_rte_dummy_exc_handler(void) {
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**************************************************************************/
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static void __neorv32_rte_debug_exc_handler(void) {
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neorv32_uart_printf("\n\n\n<<< NEORV32 Runtime Environment >>>\n");
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neorv32_uart_printf("\n\n<< NEORV32 Runtime Environment >>\n");
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neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME));
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uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t return_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST);
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if (exc_cause & 0x80000000) {
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neorv32_uart_printf("INTERRUPT");
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}
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else {
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neorv32_uart_printf("EXCEPTION");
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if ((trans_cmd & (1 << 1)) == 0) {
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return_addr -= 4;
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}
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else {
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return_addr -= 2;
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}
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}
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neorv32_uart_printf(" at instruction address: 0x%x\n", neorv32_cpu_csr_read(CSR_MEPC));
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neorv32_uart_printf(" at instruction address: 0x%x\n", return_addr);
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neorv32_uart_printf("Cause: ");
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switch (exc_cause) {
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@ -190,15 +200,176 @@ static void __neorv32_rte_debug_exc_handler(void) {
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neorv32_uart_printf("\nFaulting address");
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}
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neorv32_uart_printf(": 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
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uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST);
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neorv32_uart_printf("Transf. instruction: 0x%x ", trans_cmd);
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if ((trans_cmd & (1 << 1)) == 0) {
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neorv32_uart_printf("(decompressed)\n");
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}
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neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MSCRATCH));
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neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC));
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neorv32_uart_printf("\n<<</NEORV32 Runtime Environment >>>\n\n\n");
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neorv32_uart_printf("\n<</NEORV32 Runtime Environment >>\n\n");
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Print hardware configuration information via UART
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**************************************************************************/
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void neorv32_rte_print_hw_config(void) {
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uint32_t tmp;
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int i;
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char c;
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neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");
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// CPU configuration
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neorv32_uart_printf("\n-- Central Processing Unit --\n");
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// HW version
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neorv32_uart_printf("Hardware version: ");
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__neorv32_rte_print_hw_version();
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neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));
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// CPU architecture
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neorv32_uart_printf("Architecture: ");
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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tmp = (tmp >> 30) & 0x03;
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if (tmp == 0) {
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neorv32_uart_printf("unknown");
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}
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if (tmp == 1) {
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neorv32_uart_printf("RV32");
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}
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if (tmp == 2) {
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neorv32_uart_printf("RV64");
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}
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if (tmp == 3) {
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neorv32_uart_printf("RV128");
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}
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// CPU extensions
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neorv32_uart_printf("\nCPU extensions: ");
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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for (i=0; i<26; i++) {
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if (tmp & (1 << i)) {
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c = (char)('A' + i);
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neorv32_uart_putc(c);
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neorv32_uart_putc(' ');
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}
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}
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neorv32_uart_printf("(0x%x)\n", tmp);
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// Performance counters
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neorv32_uart_printf("CNT & time CSRs: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS));
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// Clock speed
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neorv32_uart_printf("Clock speed: %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK));
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// Memory configuration
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neorv32_uart_printf("\n-- Memory Configuration --\n");
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uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE);
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uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE);
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neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
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neorv32_uart_printf("Internal IMEM: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM));
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neorv32_uart_printf("Internal IMEM as ROM: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM));
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size = neorv32_cpu_csr_read(CSR_MDSPACESIZE);
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base = neorv32_cpu_csr_read(CSR_MDSPACEBASE);
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neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base);
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neorv32_uart_printf("Internal DMEM: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM));
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neorv32_uart_printf("Bootloader: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER));
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neorv32_uart_printf("External interface: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT));
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// peripherals
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neorv32_uart_printf("\n-- Peripherals --\n");
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tmp = neorv32_cpu_csr_read(CSR_MFEATURES);
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neorv32_uart_printf("GPIO: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));
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neorv32_uart_printf("MTIME: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));
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neorv32_uart_printf("UART: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));
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neorv32_uart_printf("SPI: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));
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neorv32_uart_printf("TWI: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));
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neorv32_uart_printf("PWM: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));
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neorv32_uart_printf("WDT: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));
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neorv32_uart_printf("CLIC: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));
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neorv32_uart_printf("TRNG: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));
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neorv32_uart_printf("DEVNULL: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Private function to print true or false.
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* @note This function is used by neorv32_rte_print_hw_config(void) only.
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*
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* @param[in] state Print TRUE when !=0, print FALSE when 0
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**************************************************************************/
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static void __neorv32_rte_print_true_false(int state) {
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if (state) {
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neorv32_uart_printf("True\n");
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}
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else {
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neorv32_uart_printf("False\n");
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}
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Private function to show the processor version in human-readable format.
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* @note This function is used by neorv32_rte_print_hw_config(void) only.
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**************************************************************************/
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static void __neorv32_rte_print_hw_version(void) {
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uint32_t i;
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char tmp, cnt;
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uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID);
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for (i=0; i<4; i++) {
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tmp = (char)(version >> (24 - 8*i));
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// serial division
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cnt = 0;
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while (tmp >= 10) {
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tmp = tmp - 10;
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cnt++;
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}
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if (cnt) {
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neorv32_uart_putc('0' + cnt);
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}
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neorv32_uart_putc('0' + tmp);
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if (i < 3) {
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neorv32_uart_putc('.');
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}
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}
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}
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