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https://github.com/stnolting/neorv32.git
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⚠️ [top] rework OCD generics
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stnolting
parent
b530b002ec
commit
b14ea49ea1
6 changed files with 62 additions and 54 deletions
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@ -455,8 +455,8 @@ This chapter gives a brief overview of all available ISA extensions.
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| <<_zmmul_isa_extension,`Zmmul`>> | Integer multiplication-only instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zmmul`>>
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| <<_zxcfu_isa_extension,`Zcfu`>> | Custom / user-defined instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zxcfu`>>
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| <<_smpmp_isa_extension,`Smpmp`>> | Physical memory protection (PMP) extension | <<_processor_top_entity_generics, `RISCV_ISA_Smpmp`>>
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| <<_sdext_isa_extension,`Sdext`>> | External debug support extension | <<_processor_top_entity_generics, `ON_CHIP_DEBUGGER_EN`>>
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| <<_sdtrig_isa_extension,`Sdtrig`>> | Trigger module extension | <<_processor_top_entity_generics, `ON_CHIP_DEBUGGER_EN`>>
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| <<_sdext_isa_extension,`Sdext`>> | External debug support extension | <<_processor_top_entity_generics, `OCD_EN`>>
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| <<_sdtrig_isa_extension,`Sdtrig`>> | Trigger module extension | <<_processor_top_entity_generics, `OCD_EN`>>
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|=======================
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.RISC-V ISA Specification
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@ -209,8 +209,9 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
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| `HART_ID` | suv(31:0) | 0x00000000 | The hart thread ID of the CPU (passed to <<_mhartid>> CSR).
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| `JEDEC_ID` | suv(10:0) | 0b00000000000 | JEDEC ID; continuation codes plus vendor ID (passed to <<_mvendorid>> CSR and to the <<_debug_transport_module_dtm>>).
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4+^| **<<_on_chip_debugger_ocd>>**
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| `ON_CHIP_DEBUGGER_EN` | boolean | false | Implement the on-chip debugger and the CPU debug mode.
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| `DM_LEGACY_MODE` | boolean | false | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode).
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| `OCD_EN` | boolean | false | Implement the on-chip debugger and the CPU debug mode.
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| `OCD_DM_LEGACY_MODE` | boolean | false | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode).
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| `OCD_AUTHENTICATION` | boolean | false | Implement on-chip debugger authentication <<_debug_authentication>> module.
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4+^| **CPU <<_instruction_sets_and_extensions>>**
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| `RISCV_ISA_C` | boolean | false | Enable <<_c_isa_extension>> (compressed instructions).
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| `RISCV_ISA_E` | boolean | false | Enable <<_e_isa_extension>> (reduced register file size).
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@ -29,7 +29,7 @@ package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100504"; -- hardware version
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100505"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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constant XLEN : natural := 32; -- native data path width
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@ -674,8 +674,9 @@ package neorv32_package is
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JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000";
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INT_BOOTLOADER_EN : boolean := false;
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN : boolean := false;
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DM_LEGACY_MODE : boolean := false;
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OCD_EN : boolean := false;
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OCD_DM_LEGACY_MODE : boolean := false;
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OCD_AUTHENTICATION : boolean := false;
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-- RISC-V CPU Extensions --
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RISCV_ISA_C : boolean := false;
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RISCV_ISA_E : boolean := false;
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@ -777,7 +778,7 @@ package neorv32_package is
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-- Global control --
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clk_i : in std_ulogic;
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rstn_i : in std_ulogic;
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-- JTAG on-chip debugger interface --
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-- JTAG on-chip debugger interface (available if OCD_EN = true) --
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jtag_tck_i : in std_ulogic := 'L';
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jtag_tdi_i : in std_ulogic := 'L';
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jtag_tdo_o : out std_ulogic;
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@ -29,8 +29,9 @@ entity neorv32_top is
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INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13
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OCD_EN : boolean := false; -- implement on-chip debugger
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OCD_DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13
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OCD_AUTHENTICATION : boolean := false; -- implement on-chip debugger authentication
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-- RISC-V CPU Extensions --
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RISCV_ISA_C : boolean := false; -- implement compressed extension
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@ -145,7 +146,7 @@ entity neorv32_top is
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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-- JTAG on-chip debugger interface (available if OCD_EN = true) --
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jtag_tck_i : in std_ulogic := 'L'; -- serial clock
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jtag_tdi_i : in std_ulogic := 'L'; -- serial data input
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jtag_tdo_o : out std_ulogic; -- serial data output
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@ -358,7 +359,8 @@ begin
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cond_sel_string_f(IO_SLINK_EN, "SLINK ", "") &
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cond_sel_string_f(IO_CRC_EN, "CRC ", "") &
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cond_sel_string_f(io_sysinfo_en_c, "SYSINFO ", "") &
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cond_sel_string_f(ON_CHIP_DEBUGGER_EN, "OCD ", "") &
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cond_sel_string_f(OCD_EN, "OCD ", "") &
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cond_sel_string_f(OCD_AUTHENTICATION, "OCD-AUTH ", "") &
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""
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severity note;
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@ -479,8 +481,8 @@ begin
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RISCV_ISA_Zksh => RISCV_ISA_Zksh,
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RISCV_ISA_Zmmul => RISCV_ISA_Zmmul,
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RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu,
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RISCV_ISA_Sdext => ON_CHIP_DEBUGGER_EN,
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RISCV_ISA_Sdtrig => ON_CHIP_DEBUGGER_EN,
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RISCV_ISA_Sdext => OCD_EN,
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RISCV_ISA_Sdtrig => OCD_EN,
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RISCV_ISA_Smpmp => cpu_smpmp_c,
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-- Tuning Options --
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FAST_MUL_EN => FAST_MUL_EN,
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@ -975,38 +977,38 @@ begin
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neorv32_bus_io_switch_inst: entity neorv32.neorv32_bus_io_switch
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generic map (
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DEV_SIZE => iodev_size_c, -- size of a single IO device
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DEV_00_EN => ON_CHIP_DEBUGGER_EN, DEV_00_BASE => base_io_dm_c,
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DEV_01_EN => io_sysinfo_en_c, DEV_01_BASE => base_io_sysinfo_c,
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DEV_02_EN => IO_NEOLED_EN, DEV_02_BASE => base_io_neoled_c,
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DEV_03_EN => io_gpio_en_c, DEV_03_BASE => base_io_gpio_c,
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DEV_04_EN => IO_WDT_EN, DEV_04_BASE => base_io_wdt_c,
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DEV_05_EN => IO_TRNG_EN, DEV_05_BASE => base_io_trng_c,
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DEV_06_EN => IO_TWI_EN, DEV_06_BASE => base_io_twi_c,
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DEV_07_EN => IO_SPI_EN, DEV_07_BASE => base_io_spi_c,
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DEV_08_EN => IO_SDI_EN, DEV_08_BASE => base_io_sdi_c,
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DEV_09_EN => IO_UART1_EN, DEV_09_BASE => base_io_uart1_c,
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DEV_10_EN => IO_UART0_EN, DEV_10_BASE => base_io_uart0_c,
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DEV_11_EN => IO_MTIME_EN, DEV_11_BASE => base_io_mtime_c,
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DEV_12_EN => io_xirq_en_c, DEV_12_BASE => base_io_xirq_c,
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DEV_13_EN => IO_ONEWIRE_EN, DEV_13_BASE => base_io_onewire_c,
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DEV_14_EN => IO_GPTMR_EN, DEV_14_BASE => base_io_gptmr_c,
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DEV_15_EN => io_pwm_en_c, DEV_15_BASE => base_io_pwm_c,
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DEV_16_EN => XIP_EN, DEV_16_BASE => base_io_xip_c,
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DEV_17_EN => IO_CRC_EN, DEV_17_BASE => base_io_crc_c,
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DEV_18_EN => IO_DMA_EN, DEV_18_BASE => base_io_dma_c,
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DEV_19_EN => IO_SLINK_EN, DEV_19_BASE => base_io_slink_c,
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DEV_20_EN => IO_CFS_EN, DEV_20_BASE => base_io_cfs_c,
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DEV_21_EN => false, DEV_31_BASE => (others => '0'), -- reserved
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DEV_22_EN => false, DEV_30_BASE => (others => '0'), -- reserved
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DEV_23_EN => false, DEV_29_BASE => (others => '0'), -- reserved
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DEV_24_EN => false, DEV_28_BASE => (others => '0'), -- reserved
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DEV_25_EN => false, DEV_27_BASE => (others => '0'), -- reserved
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DEV_26_EN => false, DEV_26_BASE => (others => '0'), -- reserved
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DEV_27_EN => false, DEV_25_BASE => (others => '0'), -- reserved
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DEV_28_EN => false, DEV_24_BASE => (others => '0'), -- reserved
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DEV_29_EN => false, DEV_23_BASE => (others => '0'), -- reserved
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DEV_30_EN => false, DEV_22_BASE => (others => '0'), -- reserved
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DEV_31_EN => false, DEV_21_BASE => (others => '0') -- reserved
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DEV_00_EN => OCD_EN, DEV_00_BASE => base_io_dm_c,
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DEV_01_EN => io_sysinfo_en_c, DEV_01_BASE => base_io_sysinfo_c,
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DEV_02_EN => IO_NEOLED_EN, DEV_02_BASE => base_io_neoled_c,
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DEV_03_EN => io_gpio_en_c, DEV_03_BASE => base_io_gpio_c,
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DEV_04_EN => IO_WDT_EN, DEV_04_BASE => base_io_wdt_c,
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DEV_05_EN => IO_TRNG_EN, DEV_05_BASE => base_io_trng_c,
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DEV_06_EN => IO_TWI_EN, DEV_06_BASE => base_io_twi_c,
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DEV_07_EN => IO_SPI_EN, DEV_07_BASE => base_io_spi_c,
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DEV_08_EN => IO_SDI_EN, DEV_08_BASE => base_io_sdi_c,
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DEV_09_EN => IO_UART1_EN, DEV_09_BASE => base_io_uart1_c,
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DEV_10_EN => IO_UART0_EN, DEV_10_BASE => base_io_uart0_c,
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DEV_11_EN => IO_MTIME_EN, DEV_11_BASE => base_io_mtime_c,
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DEV_12_EN => io_xirq_en_c, DEV_12_BASE => base_io_xirq_c,
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DEV_13_EN => IO_ONEWIRE_EN, DEV_13_BASE => base_io_onewire_c,
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DEV_14_EN => IO_GPTMR_EN, DEV_14_BASE => base_io_gptmr_c,
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DEV_15_EN => io_pwm_en_c, DEV_15_BASE => base_io_pwm_c,
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DEV_16_EN => XIP_EN, DEV_16_BASE => base_io_xip_c,
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DEV_17_EN => IO_CRC_EN, DEV_17_BASE => base_io_crc_c,
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DEV_18_EN => IO_DMA_EN, DEV_18_BASE => base_io_dma_c,
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DEV_19_EN => IO_SLINK_EN, DEV_19_BASE => base_io_slink_c,
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DEV_20_EN => IO_CFS_EN, DEV_20_BASE => base_io_cfs_c,
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DEV_21_EN => false, DEV_31_BASE => (others => '0'), -- reserved
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DEV_22_EN => false, DEV_30_BASE => (others => '0'), -- reserved
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DEV_23_EN => false, DEV_29_BASE => (others => '0'), -- reserved
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DEV_24_EN => false, DEV_28_BASE => (others => '0'), -- reserved
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DEV_25_EN => false, DEV_27_BASE => (others => '0'), -- reserved
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DEV_26_EN => false, DEV_26_BASE => (others => '0'), -- reserved
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DEV_27_EN => false, DEV_25_BASE => (others => '0'), -- reserved
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DEV_28_EN => false, DEV_24_BASE => (others => '0'), -- reserved
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DEV_29_EN => false, DEV_23_BASE => (others => '0'), -- reserved
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DEV_30_EN => false, DEV_22_BASE => (others => '0'), -- reserved
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DEV_31_EN => false, DEV_21_BASE => (others => '0') -- reserved
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)
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port map (
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clk_i => clk_i,
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@ -1570,7 +1572,8 @@ begin
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XIP_CACHE_EN => XIP_CACHE_EN,
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XIP_CACHE_NUM_BLOCKS => XIP_CACHE_NUM_BLOCKS,
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XIP_CACHE_BLOCK_SIZE => XIP_CACHE_BLOCK_SIZE,
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ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN,
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ON_CHIP_DEBUGGER_EN => OCD_EN,
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OCD_AUTHENTICATION => OCD_AUTHENTICATION,
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IO_GPIO_EN => io_gpio_en_c,
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IO_MTIME_EN => IO_MTIME_EN,
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IO_UART0_EN => IO_UART0_EN,
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@ -1611,7 +1614,7 @@ begin
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-- On-Chip Debugger Complex
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-- **************************************************************************************************************************
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neorv32_ocd_inst_true:
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if ON_CHIP_DEBUGGER_EN generate
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if OCD_EN generate
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-- On-Chip Debugger - Debug Transport Module (DTM) ----------------------------------------
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-- -------------------------------------------------------------------------------------------
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@ -1637,7 +1640,8 @@ begin
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neorv32_debug_dm_inst: entity neorv32.neorv32_debug_dm
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generic map (
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CPU_BASE_ADDR => base_io_dm_c,
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LEGACY_MODE => DM_LEGACY_MODE
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LEGACY_MODE => OCD_DM_LEGACY_MODE,
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AUTHENTICATOR => OCD_AUTHENTICATION
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)
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port map (
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clk_i => clk_i,
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@ -1654,7 +1658,7 @@ begin
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end generate;
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neorv32_debug_ocd_inst_false:
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if not ON_CHIP_DEBUGGER_EN generate
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if not OCD_EN generate
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iodev_rsp(IODEV_OCD) <= rsp_terminate_c;
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jtag_tdo_o <= jtag_tdi_i; -- JTAG pass-through
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dci_ndmrstn <= '1';
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@ -198,7 +198,8 @@ begin
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JEDEC_ID => "00000000000", -- vendor's JEDEC ID
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INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger
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OCD_EN => true, -- implement on-chip debugger
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OCD_AUTHENTICATION => true, -- implement on-chip debugger authentication
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-- RISC-V CPU Extensions --
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RISCV_ISA_C => true, -- implement compressed extension?
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RISCV_ISA_E => false, -- implement embedded RF extension?
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@ -295,7 +296,7 @@ begin
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-- Global control --
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clk_i => clk_gen, -- global clock, rising edge
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rstn_i => rst_gen, -- global reset, low-active, async
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-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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-- JTAG on-chip debugger interface (available if OCD_EN = true) --
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jtag_tck_i => '0', -- serial clock
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jtag_tdi_i => '0', -- serial data input
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jtag_tdo_o => open, -- serial data output
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@ -170,7 +170,8 @@ begin
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JEDEC_ID => "00000000000", -- vendor's JEDEC ID
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INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger
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OCD_EN => true, -- implement on-chip debugger
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OCD_AUTHENTICATION => true, -- implement on-chip debugger authentication
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-- RISC-V CPU Extensions --
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RISCV_ISA_C => false, -- implement compressed extension?
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RISCV_ISA_E => false, -- implement embedded RF extension?
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@ -271,7 +272,7 @@ begin
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-- Global control --
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clk_i => clk_gen, -- global clock, rising edge
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rstn_i => rst_gen, -- global reset, low-active, async
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-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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-- JTAG on-chip debugger interface (available if OCD_EN = true) --
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jtag_tck_i => '0', -- serial clock
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jtag_tdi_i => '0', -- serial data input
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jtag_tdo_o => open, -- serial data output
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