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[mepc] use CPU BOOT_ADDR as reset value

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stnolting 2024-11-01 14:34:21 +01:00
parent cbfd4730de
commit b3155be575
2 changed files with 2 additions and 2 deletions
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2
docs/datasheet/cpu_csr.adoc
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@ -360,7 +360,7 @@ As software does not need to determine the interrupt cause the reduction in late
|======================= |=======================
| Name | Machine exception program counter | Name | Machine exception program counter
| Address | `0x341` | Address | `0x341`
| Reset value | `0x00000000` | Reset value | `BOOT_ADDR` (CPU boot address, see <<_cpu_top_entity_generics>>)
| ISA | `Zicsr` | ISA | `Zicsr`
| Description | The `mepc` CSR provides the instruction address where execution has stopped/failed when | Description | The `mepc` CSR provides the instruction address where execution has stopped/failed when
an interrupt is triggered / an exception is raised. See section <<_traps_exceptions_and_interrupts>> for a list of all legal values. an interrupt is triggered / an exception is raised. See section <<_traps_exceptions_and_interrupts>> for a list of all legal values.

2
rtl/core/neorv32_cpu_control.vhd
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@ -1410,7 +1410,7 @@ begin
csr.mie_firq <= (others => '0'); csr.mie_firq <= (others => '0');
csr.mtvec <= (others => '0'); csr.mtvec <= (others => '0');
csr.mscratch <= x"19880704"; csr.mscratch <= x"19880704";
csr.mepc <= (others => '0'); csr.mepc <= BOOT_ADDR(XLEN-1 downto 2) & "00"; -- 32-bit-aligned boot address
csr.mcause <= (others => '0'); csr.mcause <= (others => '0');
csr.mtval <= (others => '0'); csr.mtval <= (others => '0');
csr.mtinst <= (others => '0'); csr.mtinst <= (others => '0');