github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-23 21:57:33 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

⚠️ [cpu] remove Zifencei generic

Browse source 
Zifencei ISA extension is now always enabled
This commit is contained in:
stnolting 2023-10-18 21:48:48 +02:00
parent cff3c3c4b3
commit b3b2124b4e
4 changed files with 256 additions and 273 deletions
Download patch file Download diff file Expand all files Collapse all files

84
rtl/core/neorv32_cpu.vhd
View file

@ -57,7 +57,6 @@ entity neorv32_cpu is
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_Sdext : boolean; -- implement external debug mode extension?
@ -146,22 +145,22 @@ begin
-- CPU ISA configuration --
assert false report
"NEORV32 CPU Configuration: RV32" &
cond_sel_string_f(CPU_EXTENSION_RISCV_E, "E", "I") &
cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_A, "A", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_B, "B", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "") &
cond_sel_string_f(true, "_Zicsr", "") & -- always enabled
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext, "_Sdext", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Sdtrig, "_Sdtrig", "") &
cond_sel_string_f(pmp_enable_c, "_Smpmp", "")
cond_sel_string_f(CPU_EXTENSION_RISCV_E, "E", "I") &
cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_A, "A", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_B, "B", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "") &
cond_sel_string_f(true, "_Zicsr", "") & -- always enabled
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "") &
cond_sel_string_f(true, "_Zifencei", "") & -- always enabled
cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext, "_Sdext", "") &
cond_sel_string_f(CPU_EXTENSION_RISCV_Sdtrig, "_Sdtrig", "") &
cond_sel_string_f(pmp_enable_c, "_Smpmp", "")
severity note;
-- simulation notifier --
@ -176,44 +175,39 @@ begin
assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report
"NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error;
-- Debug mode --
assert not ((CPU_EXTENSION_RISCV_Sdext = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report
"NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zifencei> extension to be enabled." severity error;
-- Control Unit ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_control_inst: entity neorv32.neorv32_cpu_control
generic map (
-- General --
HART_ID => HART_ID, -- hardware thread ID
VENDOR_ID => VENDOR_ID, -- vendor's JEDEC ID
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
CPU_DEBUG_PARK_ADDR => CPU_DEBUG_PARK_ADDR, -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR => CPU_DEBUG_EXC_ADDR, -- cpu debug mode exception entry address
HART_ID => HART_ID, -- hardware thread ID
VENDOR_ID => VENDOR_ID, -- vendor's JEDEC ID
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
CPU_DEBUG_PARK_ADDR => CPU_DEBUG_PARK_ADDR, -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR => CPU_DEBUG_EXC_ADDR, -- cpu debug mode exception entry address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_Sdext => CPU_EXTENSION_RISCV_Sdext, -- implement external debug mode extension?
CPU_EXTENSION_RISCV_Sdtrig => CPU_EXTENSION_RISCV_Sdtrig, -- implement trigger module extension?
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_Sdext => CPU_EXTENSION_RISCV_Sdext, -- implement external debug mode extension?
CPU_EXTENSION_RISCV_Sdtrig => CPU_EXTENSION_RISCV_Sdtrig, -- implement trigger module extension?
-- Tuning Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
-- Physical memory protection (PMP) --
PMP_EN => pmp_enable_c, -- physical memory protection enabled
PMP_EN => pmp_enable_c, -- physical memory protection enabled
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..13)
HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..13)
HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters
)
port map (
-- global control --

88
rtl/core/neorv32_cpu_control.vhd
View file

@ -53,34 +53,33 @@ use neorv32.neorv32_package.all;
entity neorv32_cpu_control is
generic (
-- General --
HART_ID : std_ulogic_vector(31 downto 0); -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
CPU_DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
HART_ID : std_ulogic_vector(31 downto 0); -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
CPU_DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT regs)
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_Sdext : boolean; -- implement external debug mode extension?
CPU_EXTENSION_RISCV_Sdtrig : boolean; -- implement trigger module extension?
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT regs)
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_Sdext : boolean; -- implement external debug mode extension?
CPU_EXTENSION_RISCV_Sdtrig : boolean; -- implement trigger module extension?
-- Tuning Options --
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
-- Physical memory protection (PMP) --
PMP_EN : boolean; -- physical memory protection enabled
PMP_EN : boolean; -- physical memory protection enabled
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural range 0 to 13; -- number of implemented HPM counters (0..13)
HPM_CNT_WIDTH : natural range 0 to 64 -- total size of HPM counters (0..64)
HPM_NUM_CNTS : natural range 0 to 13; -- number of implemented HPM counters (0..13)
HPM_CNT_WIDTH : natural range 0 to 64 -- total size of HPM counters (0..64)
);
port (
-- global control --
@ -980,12 +979,10 @@ begin
-- ------------------------------------------------------------
if (trap_ctrl.exc_buf(exc_illegal_c) = '1') then -- abort if illegal instruction
execute_engine.state_nxt <= DISPATCH;
elsif (execute_engine.ir(instr_funct3_lsb_c) = funct3_fencei_c(0)) and (CPU_EXTENSION_RISCV_Zifencei = true) then
ctrl_nxt.lsu_fencei <= '1'; -- instruction fence
execute_engine.state_nxt <= RESTART; -- reset instruction fetch + IPB
else
ctrl_nxt.lsu_fence <= '1'; -- data fence
execute_engine.state_nxt <= DISPATCH;
ctrl_nxt.lsu_fence <= not execute_engine.ir(instr_funct3_lsb_c); -- data: fence
ctrl_nxt.lsu_fencei <= execute_engine.ir(instr_funct3_lsb_c); -- instruction: fence.i
execute_engine.state_nxt <= RESTART; -- reset instruction fetch + IPB (only required for fence.i)
end if;
when BRANCH => -- update PC on taken branches and jumps
@ -1310,9 +1307,8 @@ begin
when opcode_fence_c =>
case execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) is
when funct3_fence_c => illegal_cmd <= '0'; -- FENCE
when funct3_fencei_c => illegal_cmd <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- FENCE.I
when others => illegal_cmd <= '1';
when funct3_fence_c | funct3_fencei_c => illegal_cmd <= '0'; -- FENCE[.I]
when others => illegal_cmd <= '1';
end case;
when opcode_system_c =>
@ -2063,23 +2059,23 @@ begin
-- machine extended ISA extensions information --
when csr_mxisa_c =>
-- extended ISA (sub-)extensions --
csr_rdata(00) <= '1'; -- Zicsr: CSR access (always enabled)
csr_rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei: instruction stream sync.
csr_rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul: mul/div
csr_rdata(03) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- Zxcfu: custom RISC-V instructions
csr_rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- Smcntrpmf: counter privilege mode filtering (enabled if U implemented)
csr_rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers
csr_rdata(00) <= '1'; -- Zicsr: CSR access (always enabled)
csr_rdata(01) <= '1'; -- Zifencei: instruction stream sync. (always enabled)
csr_rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul: mul/div
csr_rdata(03) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- Zxcfu: custom RISC-V instructions
csr_rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- Smcntrpmf: counter privilege mode filtering (enabled if U implemented)
csr_rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers
-- csr_rdata(06) <= '0'; -- reserved
csr_rdata(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base counters
csr_rdata(08) <= bool_to_ulogic_f(PMP_EN); -- PMP: physical memory protection (Smpmp)
csr_rdata(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- Zihpm: hardware performance monitors
csr_rdata(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Sdext); -- Sdext: RISC-V (external) debug mode
csr_rdata(11) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Sdtrig); -- Sdtrig: trigger module
csr_rdata(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base counters
csr_rdata(08) <= bool_to_ulogic_f(PMP_EN); -- PMP: physical memory protection (Smpmp)
csr_rdata(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- Zihpm: hardware performance monitors
csr_rdata(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Sdext); -- Sdext: RISC-V (external) debug mode
csr_rdata(11) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Sdtrig); -- Sdtrig: trigger module
-- misc --
csr_rdata(20) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
csr_rdata(20) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
-- tuning options --
csr_rdata(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extensions only)
csr_rdata(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters)
csr_rdata(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extensions only)
csr_rdata(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters)
-- undefined/unavailable (or implemented externally) --
-- --------------------------------------------------------------------

153
rtl/core/neorv32_package.vhd
View file

@ -59,7 +59,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090002"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090003"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width, do not change!
@ -746,95 +746,94 @@ package neorv32_package is
component neorv32_top
generic (
-- General --
CLOCK_FREQUENCY : natural;
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000";
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000";
INT_BOOTLOADER_EN : boolean := false;
CLOCK_FREQUENCY : natural;
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000";
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000";
INT_BOOTLOADER_EN : boolean := false;
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN : boolean := false;
DM_LEGACY_MODE : boolean := false;
ON_CHIP_DEBUGGER_EN : boolean := false;
DM_LEGACY_MODE : boolean := false;
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false;
CPU_EXTENSION_RISCV_B : boolean := false;
CPU_EXTENSION_RISCV_C : boolean := false;
CPU_EXTENSION_RISCV_E : boolean := false;
CPU_EXTENSION_RISCV_M : boolean := false;
CPU_EXTENSION_RISCV_U : boolean := false;
CPU_EXTENSION_RISCV_Zfinx : boolean := false;
CPU_EXTENSION_RISCV_Zicntr : boolean := true;
CPU_EXTENSION_RISCV_Zihpm : boolean := false;
CPU_EXTENSION_RISCV_Zifencei : boolean := false;
CPU_EXTENSION_RISCV_Zmmul : boolean := false;
CPU_EXTENSION_RISCV_Zxcfu : boolean := false;
CPU_EXTENSION_RISCV_A : boolean := false;
CPU_EXTENSION_RISCV_B : boolean := false;
CPU_EXTENSION_RISCV_C : boolean := false;
CPU_EXTENSION_RISCV_E : boolean := false;
CPU_EXTENSION_RISCV_M : boolean := false;
CPU_EXTENSION_RISCV_U : boolean := false;
CPU_EXTENSION_RISCV_Zfinx : boolean := false;
CPU_EXTENSION_RISCV_Zicntr : boolean := true;
CPU_EXTENSION_RISCV_Zihpm : boolean := false;
CPU_EXTENSION_RISCV_Zmmul : boolean := false;
CPU_EXTENSION_RISCV_Zxcfu : boolean := false;
-- Tuning Options --
FAST_MUL_EN : boolean := false;
FAST_SHIFT_EN : boolean := false;
FAST_MUL_EN : boolean := false;
FAST_SHIFT_EN : boolean := false;
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural range 0 to 16 := 0;
PMP_MIN_GRANULARITY : natural := 4;
PMP_NUM_REGIONS : natural range 0 to 16 := 0;
PMP_MIN_GRANULARITY : natural := 4;
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural range 0 to 13 := 0;
HPM_CNT_WIDTH : natural range 0 to 64 := 40;
HPM_NUM_CNTS : natural range 0 to 13 := 0;
HPM_CNT_WIDTH : natural range 0 to 64 := 40;
-- Atomic Memory Access - Reservation Set Granularity --
AMO_RVS_GRANULARITY : natural := 4;
AMO_RVS_GRANULARITY : natural := 4;
-- Internal Instruction memory (IMEM) --
MEM_INT_IMEM_EN : boolean := false;
MEM_INT_IMEM_SIZE : natural := 16*1024;
MEM_INT_IMEM_EN : boolean := false;
MEM_INT_IMEM_SIZE : natural := 16*1024;
-- Internal Data memory (DMEM) --
MEM_INT_DMEM_EN : boolean := false;
MEM_INT_DMEM_SIZE : natural := 8*1024;
MEM_INT_DMEM_EN : boolean := false;
MEM_INT_DMEM_SIZE : natural := 8*1024;
-- Internal Instruction Cache (iCACHE) --
ICACHE_EN : boolean := false;
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
ICACHE_ASSOCIATIVITY : natural range 1 to 2 := 1;
ICACHE_EN : boolean := false;
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
ICACHE_ASSOCIATIVITY : natural range 1 to 2 := 1;
-- Internal Data Cache (dCACHE) --
DCACHE_EN : boolean := false;
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
DCACHE_EN : boolean := false;
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4;
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64;
-- External memory interface (WISHBONE) --
MEM_EXT_EN : boolean := false;
MEM_EXT_TIMEOUT : natural := 255;
MEM_EXT_PIPE_MODE : boolean := false;
MEM_EXT_BIG_ENDIAN : boolean := false;
MEM_EXT_ASYNC_RX : boolean := false;
MEM_EXT_ASYNC_TX : boolean := false;
MEM_EXT_EN : boolean := false;
MEM_EXT_TIMEOUT : natural := 255;
MEM_EXT_PIPE_MODE : boolean := false;
MEM_EXT_BIG_ENDIAN : boolean := false;
MEM_EXT_ASYNC_RX : boolean := false;
MEM_EXT_ASYNC_TX : boolean := false;
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural range 0 to 32 := 0;
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff";
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff";
XIRQ_NUM_CH : natural range 0 to 32 := 0;
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff";
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff";
-- Processor peripherals --
IO_GPIO_NUM : natural range 0 to 64 := 0;
IO_MTIME_EN : boolean := false;
IO_UART0_EN : boolean := false;
IO_UART0_RX_FIFO : natural range 1 to 2**15 := 1;
IO_UART0_TX_FIFO : natural range 1 to 2**15 := 1;
IO_UART1_EN : boolean := false;
IO_UART1_RX_FIFO : natural range 1 to 2**15 := 1;
IO_UART1_TX_FIFO : natural range 1 to 2**15 := 1;
IO_SPI_EN : boolean := false;
IO_SPI_FIFO : natural range 1 to 2**15 := 1;
IO_SDI_EN : boolean := false;
IO_SDI_FIFO : natural range 1 to 2**15 := 1;
IO_TWI_EN : boolean := false;
IO_PWM_NUM_CH : natural range 0 to 12 := 0;
IO_WDT_EN : boolean := false;
IO_TRNG_EN : boolean := false;
IO_TRNG_FIFO : natural range 1 to 2**15 := 1;
IO_CFS_EN : boolean := false;
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000";
IO_CFS_IN_SIZE : natural := 32;
IO_CFS_OUT_SIZE : natural := 32;
IO_NEOLED_EN : boolean := false;
IO_NEOLED_TX_FIFO : natural range 1 to 2**15 := 1;
IO_GPTMR_EN : boolean := false;
IO_XIP_EN : boolean := false;
IO_ONEWIRE_EN : boolean := false;
IO_DMA_EN : boolean := false;
IO_SLINK_EN : boolean := false;
IO_SLINK_RX_FIFO : natural range 1 to 2**15 := 1;
IO_SLINK_TX_FIFO : natural range 1 to 2**15 := 1;
IO_CRC_EN : boolean := false
IO_GPIO_NUM : natural range 0 to 64 := 0;
IO_MTIME_EN : boolean := false;
IO_UART0_EN : boolean := false;
IO_UART0_RX_FIFO : natural range 1 to 2**15 := 1;
IO_UART0_TX_FIFO : natural range 1 to 2**15 := 1;
IO_UART1_EN : boolean := false;
IO_UART1_RX_FIFO : natural range 1 to 2**15 := 1;
IO_UART1_TX_FIFO : natural range 1 to 2**15 := 1;
IO_SPI_EN : boolean := false;
IO_SPI_FIFO : natural range 1 to 2**15 := 1;
IO_SDI_EN : boolean := false;
IO_SDI_FIFO : natural range 1 to 2**15 := 1;
IO_TWI_EN : boolean := false;
IO_PWM_NUM_CH : natural range 0 to 12 := 0;
IO_WDT_EN : boolean := false;
IO_TRNG_EN : boolean := false;
IO_TRNG_FIFO : natural range 1 to 2**15 := 1;
IO_CFS_EN : boolean := false;
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000";
IO_CFS_IN_SIZE : natural := 32;
IO_CFS_OUT_SIZE : natural := 32;
IO_NEOLED_EN : boolean := false;
IO_NEOLED_TX_FIFO : natural range 1 to 2**15 := 1;
IO_GPTMR_EN : boolean := false;
IO_XIP_EN : boolean := false;
IO_ONEWIRE_EN : boolean := false;
IO_DMA_EN : boolean := false;
IO_SLINK_EN : boolean := false;
IO_SLINK_RX_FIFO : natural range 1 to 2**15 := 1;
IO_SLINK_TX_FIFO : natural range 1 to 2**15 := 1;
IO_CRC_EN : boolean := false
);
port (
-- Global control --

204
rtl/core/neorv32_top.vhd
View file

@ -47,108 +47,107 @@ use neorv32.neorv32_package.all;
entity neorv32_top is
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic memory operations extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
-- Tuning Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural range 0 to 16 := 0; -- number of regions (0..16)
PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
PMP_NUM_REGIONS : natural range 0 to 16 := 0; -- number of regions (0..16)
PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural range 0 to 13 := 0; -- number of implemented HPM counters (0..13)
HPM_CNT_WIDTH : natural range 0 to 64 := 40; -- total size of HPM counters (0..64)
HPM_NUM_CNTS : natural range 0 to 13 := 0; -- number of implemented HPM counters (0..13)
HPM_CNT_WIDTH : natural range 0 to 64 := 40; -- total size of HPM counters (0..64)
-- Atomic Memory Access - Reservation Set Granularity --
AMO_RVS_GRANULARITY : natural := 4; -- size in bytes, has to be a power of 2, min 4
AMO_RVS_GRANULARITY : natural := 4; -- size in bytes, has to be a power of 2, min 4
-- Internal Instruction memory (IMEM) --
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes (use a power of 2)
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes (use a power of 2)
-- Internal Data memory (DMEM) --
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes (use a power of 2)
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes (use a power of 2)
-- Internal Instruction Cache (iCACHE) --
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural range 1 to 2 := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural range 1 to 256 := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural range 1 to 2 := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- Internal Data Cache (dCACHE) --
DCACHE_EN : boolean := false; -- implement data cache
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
DCACHE_EN : boolean := false; -- implement data cache
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
-- External memory interface (WISHBONE) --
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false
MEM_EXT_ASYNC_TX : boolean := false; -- use register buffer for TX data when false
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false
MEM_EXT_ASYNC_TX : boolean := false; -- use register buffer for TX data when false
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural range 0 to 32 := 0; -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
XIRQ_NUM_CH : natural range 0 to 32 := 0; -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
-- Processor peripherals --
IO_GPIO_NUM : natural range 0 to 64 := 0; -- number of GPIO input/output pairs (0..64)
IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART0_RX_FIFO : natural range 1 to 2**15 := 1; -- RX fifo depth, has to be a power of two, min 1
IO_UART0_TX_FIFO : natural range 1 to 2**15 := 1; -- TX fifo depth, has to be a power of two, min 1
IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_UART1_RX_FIFO : natural range 1 to 2**15 := 1; -- RX fifo depth, has to be a power of two, min 1
IO_UART1_TX_FIFO : natural range 1 to 2**15 := 1; -- TX fifo depth, has to be a power of two, min 1
IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
IO_SPI_FIFO : natural range 1 to 2**15 := 1; -- RTX fifo depth, has to be a power of two, min 1
IO_SDI_EN : boolean := false; -- implement serial data interface (SDI)?
IO_SDI_FIFO : natural range 1 to 2**15 := 1; -- RTX fifo depth, has to be zero or a power of two, min 1
IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural range 0 to 12 := 0; -- number of PWM channels to implement (0..12); 0 = disabled
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_TRNG_FIFO : natural range 1 to 2**15 := 1; -- data fifo depth, has to be a power of two, min 1
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : natural := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : natural := 32; -- size of CFS output conduit in bits
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural range 1 to 2**15 := 1; -- NEOLED FIFO depth, has to be a power of two, min 1
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)?
IO_DMA_EN : boolean := false; -- implement direct memory access controller (DMA)?
IO_SLINK_EN : boolean := false; -- implement stream link interface (SLINK)?
IO_SLINK_RX_FIFO : natural range 1 to 2**15 := 1; -- RX fifo depth, has to be a power of two, min 1
IO_SLINK_TX_FIFO : natural range 1 to 2**15 := 1; -- TX fifo depth, has to be a power of two, min 1
IO_CRC_EN : boolean := false -- implement cyclic redundancy check unit (CRC)?
IO_GPIO_NUM : natural range 0 to 64 := 0; -- number of GPIO input/output pairs (0..64)
IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART0_RX_FIFO : natural range 1 to 2**15 := 1; -- RX fifo depth, has to be a power of two, min 1
IO_UART0_TX_FIFO : natural range 1 to 2**15 := 1; -- TX fifo depth, has to be a power of two, min 1
IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_UART1_RX_FIFO : natural range 1 to 2**15 := 1; -- RX fifo depth, has to be a power of two, min 1
IO_UART1_TX_FIFO : natural range 1 to 2**15 := 1; -- TX fifo depth, has to be a power of two, min 1
IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
IO_SPI_FIFO : natural range 1 to 2**15 := 1; -- RTX fifo depth, has to be a power of two, min 1
IO_SDI_EN : boolean := false; -- implement serial data interface (SDI)?
IO_SDI_FIFO : natural range 1 to 2**15 := 1; -- RTX fifo depth, has to be zero or a power of two, min 1
IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural range 0 to 12 := 0; -- number of PWM channels to implement (0..12); 0 = disabled
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_TRNG_FIFO : natural range 1 to 2**15 := 1; -- data fifo depth, has to be a power of two, min 1
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : natural := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : natural := 32; -- size of CFS output conduit in bits
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural range 1 to 2**15 := 1; -- NEOLED FIFO depth, has to be a power of two, min 1
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)?
IO_DMA_EN : boolean := false; -- implement direct memory access controller (DMA)?
IO_SLINK_EN : boolean := false; -- implement stream link interface (SLINK)?
IO_SLINK_RX_FIFO : natural range 1 to 2**15 := 1; -- RX fifo depth, has to be a power of two, min 1
IO_SLINK_TX_FIFO : natural range 1 to 2**15 := 1; -- TX fifo depth, has to be a power of two, min 1
IO_CRC_EN : boolean := false -- implement cyclic redundancy check unit (CRC)?
);
port (
-- Global control --
@ -380,10 +379,6 @@ begin
"NEORV32 PROCESSOR CONFIG WARNING: Configured internal DMEM size (" & natural'image(MEM_INT_DMEM_SIZE) & " bytes) is not a power of two. " &
"Auto-adjusting memory size to the next power of two (" & natural'image(dmem_size_c) & " bytes)" severity warning;
-- caches --
assert not ((ICACHE_EN = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report
"NEORV32 CPU CONFIG ERROR: <CPU_EXTENSION_RISCV_Zifencei> ISA extension is required to perform i-cache memory sync. operations." severity error;
end generate; -- /sanity_checks
@ -480,35 +475,34 @@ begin
neorv32_cpu_inst: entity neorv32.neorv32_cpu
generic map (
-- General --
HART_ID => HART_ID,
VENDOR_ID => VENDOR_ID,
CPU_BOOT_ADDR => cpu_boot_addr_c,
CPU_DEBUG_PARK_ADDR => dm_park_entry_c,
CPU_DEBUG_EXC_ADDR => dm_exc_entry_c,
HART_ID => HART_ID,
VENDOR_ID => VENDOR_ID,
CPU_BOOT_ADDR => cpu_boot_addr_c,
CPU_DEBUG_PARK_ADDR => dm_park_entry_c,
CPU_DEBUG_EXC_ADDR => dm_exc_entry_c,
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A,
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B,
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C,
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E,
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M,
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U,
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx,
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm,
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei,
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul,
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu,
CPU_EXTENSION_RISCV_Sdext => ON_CHIP_DEBUGGER_EN,
CPU_EXTENSION_RISCV_Sdtrig => ON_CHIP_DEBUGGER_EN,
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A,
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B,
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C,
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E,
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M,
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U,
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx,
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm,
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul,
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu,
CPU_EXTENSION_RISCV_Sdext => ON_CHIP_DEBUGGER_EN,
CPU_EXTENSION_RISCV_Sdtrig => ON_CHIP_DEBUGGER_EN,
-- Tuning Options --
FAST_MUL_EN => FAST_MUL_EN,
FAST_SHIFT_EN => FAST_SHIFT_EN,
FAST_MUL_EN => FAST_MUL_EN,
FAST_SHIFT_EN => FAST_SHIFT_EN,
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS => PMP_NUM_REGIONS,
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY,
PMP_NUM_REGIONS => PMP_NUM_REGIONS,
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY,
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => HPM_NUM_CNTS,
HPM_CNT_WIDTH => HPM_CNT_WIDTH
HPM_NUM_CNTS => HPM_NUM_CNTS,
HPM_CNT_WIDTH => HPM_CNT_WIDTH
)
port map (
-- global control --