github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-19 11:55:05 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

🐛 fix PWM prescaler (#1222)
Some checks failed
Processor / processor simulation (push) Has been cancelled
Details

Browse source
This commit is contained in:
stnolting 2025-04-01 17:38:47 +02:00 • committed by GitHub
commit b562f09999
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
3 changed files with 6 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
CHANGELOG.md
View file

@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 01.04.2025 | 1.11.2.4 | :bug: fix bug in PWM clock prescaler | [#1222](https://github.com/stnolting/neorv32/pull/1222) |
| 29.03.2025 | 1.11.2.3 | :sparkles: add optional 32 hardware spinlocks (`HWSPINLOCK` module) | [#1220](https://github.com/stnolting/neorv32/pull/1220) |
| 24.03.2025 | 1.11.2.2 | TWD: add separate RX/TX FIFO configuration; add dummy response (if TX FIFO is empty); add optional no-ACK on read access if TX FIFO is empty | [#1210](https://github.com/stnolting/neorv32/pull/1210) |
| 21.03.2025 | 1.11.2.1 | :warning: remove clock gating option | [#1214](https://github.com/stnolting/neorv32/pull/1214) |

2
rtl/core/neorv32_package.vhd
View file

@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110203"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110204"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

8
rtl/core/neorv32_pwm.vhd
View file

@ -198,17 +198,20 @@ begin
pwm_core: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
cnt_tick <= '0';
cnt_cdiv <= (others => '0');
cnt_duty <= (others => '0');
pwm_o <= '0';
elsif rising_edge(clk_i) then
-- clock divider --
cnt_tick <= '0'; -- default
if (cfg_en = '0') then
cnt_cdiv <= (others => '0');
elsif (clkgen_i(to_integer(unsigned(cfg_prsc))) = '1') then -- pre-scaled clock (coarse)
if (cnt_tick = '1') then -- fine-tuned clock
if (cnt_cdiv = cfg_cdiv) then -- fine-tuned clock
cnt_cdiv <= (others => '0');
cnt_tick <= '1'; -- single-shot
else
cnt_cdiv <= std_ulogic_vector(unsigned(cnt_cdiv) + 1);
end if;
@ -231,7 +234,4 @@ begin
end if;
end process pwm_core;
-- fine-tuned clock tick --
cnt_tick <= '1' when (cnt_cdiv = cfg_cdiv) else '0';
end neorv32_pwm_channel_rtl;