mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-24 14:17:51 -04:00
[sw] remove AMO emulation layer
no we have "real" AMOs
This commit is contained in:
stnolting
parent
b167053295
commit
b677f49af7
6 changed files with 0 additions and 829 deletions
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@ -67,7 +67,6 @@ The NEORV32 HAL consists of the following files.
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| `neorv32_cfs.c` | `neorv32_cfs.h` | <<_custom_functions_subsystem_cfs>> HAL
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| `neorv32_clint.c` | `neorv32_clint.h` | <<_core_local_interruptor_clint>> HAL
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| `neorv32_cpu.c` | `neorv32_cpu.h` | <<_neorv32_central_processing_unit_cpu>> HAL
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| `neorv32_cpu_amo.c` | `neorv32_cpu_amo.h` | Emulation functions for the read-modify-write <<_zalrsc_isa_extension>> / `A` instructions
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| | `neorv32_cpu_csr.h` | <<_control_and_status_registers_csrs>> definitions
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| `neorv32_cpu_cfu.c` | `neorv32_cpu_cfu.h` | <<_custom_functions_unit_cfu>> HAL
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| `neorv32_crc.c` | `neorv32_crc.h` | <<_cyclic_redundancy_check_crc>> HAL
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@ -1,363 +0,0 @@
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// ================================================================================ //
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// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
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// Copyright (c) NEORV32 contributors. //
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// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //
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// Licensed under the BSD-3-Clause license, see LICENSE for details. //
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// SPDX-License-Identifier: BSD-3-Clause //
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// ================================================================================ //
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/**********************************************************************//**
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* @file atomic_test/main.c
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* @author Stephan Nolting
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* @brief Test program for the NEORV32 'A' ISA extension - check the emulation
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* of the AMO (read-modify-write) operations.
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**************************************************************************/
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#include <neorv32.h>
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/**********************************************************************//**
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* @name User configuration
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**************************************************************************/
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/**@{*/
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/** UART BAUD rate */
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#define BAUD_RATE (19200)
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//** Number of test cases for each instruction */
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#define NUM_TEST_CASES (1000)
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//** Silent mode (only show actual errors when != 0) */
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#define SILENT_MODE (1)
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// Prototypes
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uint32_t check_result(uint32_t num, uint32_t amo_var_old, uint32_t amo_var_pre, uint32_t amo_var_new, uint32_t amo_var);
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void print_report(int num_err, int num_tests);
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// Global variable for atomic accesses
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volatile uint32_t amo_var;
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/**********************************************************************//**
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* Emulate atomic memory operation.
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*
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* @note This is a RTE "second-level" trap handler.
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**************************************************************************/
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void trap_handler_emulate_amo(void) {
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uint32_t inst = neorv32_cpu_csr_read(CSR_MTINST);
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// decompose I-type instruction
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uint32_t opcode = (inst >> 0) & 0x07f;
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uint32_t rd_addr = (inst >> 7) & 0x01f;
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uint32_t funct3 = (inst >> 12) & 0x003;
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uint32_t rs1_addr = (inst >> 15) & 0x01f;
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uint32_t rs2_addr = (inst >> 20) & 0x01f;
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uint32_t funct5 = (inst >> 27) & 0x01f;
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// set opcode bit 1 as the instruction word might be transformed (de-compressed)
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opcode |= 1 << 1;
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#if 0
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neorv32_uart0_printf("\n<< EMULATING >>\n");
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neorv32_uart0_printf(" opcode: 0x%x\n", opcode);
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neorv32_uart0_printf(" rd_addr: %u\n", rd_addr);
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neorv32_uart0_printf(" funct3: %u\n", funct3);
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neorv32_uart0_printf(" rs1_addr: %u\n", rs1_addr);
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neorv32_uart0_printf(" rs2_addr: %u\n", rs2_addr);
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neorv32_uart0_printf(" funct5: 0x%x\n", funct5);
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neorv32_uart0_printf("<< /EMULATING >>\n\n");
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#endif
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// emulate if valid A operation and A ISA extension is available
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if ((opcode == 0b0101111) && (funct3 == 0b010) && (neorv32_cpu_csr_read(CSR_MISA) & (1 << 0))) {
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// get operands from main's context
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uint32_t rs1 = neorv32_rte_context_get(rs1_addr);
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uint32_t rs2 = neorv32_rte_context_get(rs2_addr);
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uint32_t rd = 0, valid = 0;
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// emulated functions
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switch (funct5) {
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case 0b00001: rd = neorv32_cpu_amoswapw(rs1, rs2); valid = 1; break; // amoswap.w
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case 0b00000: rd = neorv32_cpu_amoaddw( rs1, rs2); valid = 1; break; // amoadd.w
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case 0b00100: rd = neorv32_cpu_amoxorw( rs1, rs2); valid = 1; break; // amoxor.w
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case 0b01100: rd = neorv32_cpu_amoandw( rs1, rs2); valid = 1; break; // amoand.w
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case 0b01000: rd = neorv32_cpu_amoorw( rs1, rs2); valid = 1; break; // amoor.w
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case 0b10000: rd = neorv32_cpu_amominw( rs1, rs2); valid = 1; break; // amomin.w
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case 0b10100: rd = neorv32_cpu_amomaxw( rs1, rs2); valid = 1; break; // amomax.w
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case 0b11000: rd = neorv32_cpu_amominuw(rs1, rs2); valid = 1; break; // amominu.w
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case 0b11100: rd = neorv32_cpu_amomaxuw(rs1, rs2); valid = 1; break; // amomaxu.w
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default: neorv32_rte_debug_handler(); break; // use the RTE debug handler for any other misaligned load exception
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}
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if (valid) {
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// write result back to main's context
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neorv32_rte_context_put(rd_addr, rd);
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}
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}
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else {
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neorv32_rte_debug_handler();
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}
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}
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/**********************************************************************//**
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* Main function; test all provided AMO emulation functions.
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*
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* @note This program requires the RISC-V A CPU extension.
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*
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* @return Irrelevant.
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**************************************************************************/
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int main() {
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const uint32_t num_tests = (uint32_t)NUM_TEST_CASES;
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// capture all exceptions and give debug info via UART
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neorv32_rte_setup();
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// install trap handler for "unaligned load address" exception
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neorv32_rte_handler_install(RTE_TRAP_I_ILLEGAL, trap_handler_emulate_amo);
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// setup UART0 at default baud rate, no interrupts
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neorv32_uart0_setup(BAUD_RATE, 0);
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// intro
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neorv32_uart0_printf("<<< NEORV32 AMO Operations (atomic read-modify-write) Emulation Test >>>\n\n");
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// check if A extension is implemented at all
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if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZALRSC)) == 0) {
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neorv32_uart0_printf("Error! A ISA extension not implemented!\n");
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return 1;
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}
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#if (SILENT_MODE != 0)
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neorv32_uart0_printf("SILENT_MODE enabled (only showing actual errors)\n");
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#endif
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neorv32_uart0_printf("Starting tests (%u test case(s) per instruction)...\n\n", num_tests);
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#if defined __riscv_atomic
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uint32_t amo_addr;
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uint32_t amo_var_old, amo_var_new, amo_var_update, amo_var_pre;
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uint32_t i = 0, err_cnt = 0;
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amo_addr = (uint32_t)&amo_var;
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// AMOSWAP.W
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neorv32_uart0_printf("\namoswap.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amoswap.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = amo_var_update;
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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// AMOADD.W
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neorv32_uart0_printf("\namoadd.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amoadd.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = amo_var_old + amo_var_update;
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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// AMOAND.W
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neorv32_uart0_printf("\namoand.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amoand.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = amo_var_old & amo_var_update;
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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// AMOOR.W
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neorv32_uart0_printf("\namoor.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amoor.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = amo_var_old | amo_var_update;
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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// AMOXOR.W
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neorv32_uart0_printf("\namoxor.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amoxor.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = amo_var_old ^ amo_var_update;
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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// AMOMAX.W
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neorv32_uart0_printf("\namomax.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amomax.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = (uint32_t)neorv32_aux_max((int32_t)amo_var_old, (int32_t)amo_var_update);
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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// AMOMAXU.W
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neorv32_uart0_printf("\namomaxu.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amomaxu.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = neorv32_aux_max(amo_var_old, amo_var_update);
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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// AMOMIN.W
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neorv32_uart0_printf("\namomin.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amomin.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = (uint32_t)neorv32_aux_min((int32_t)amo_var_old, (int32_t)amo_var_update);
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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// AMOMINU.W
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neorv32_uart0_printf("\namominu.w:\n");
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err_cnt = 0;
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for (i=0; i<num_tests; i++) {
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amo_var_old = neorv32_aux_xorshift32();
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amo_var_update = neorv32_aux_xorshift32();
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amo_var = amo_var_old;
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asm volatile ("fence");
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asm volatile ("amominu.w %[dest], %[data], 0(%[addr])" : [dest] "=r" (amo_var_pre) : [data] "r" (amo_var_update), [addr] "r" (amo_addr));
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asm volatile ("fence");
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amo_var_new = neorv32_aux_min(amo_var_old, amo_var_update);
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err_cnt += check_result(i, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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}
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print_report(err_cnt, num_tests);
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#else
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#warning Program HAS NOT BEEN COMPILED since RISC-V 'A' ISA extension is not enabled!
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neorv32_uart0_printf("\nProgram HAS NOT BEEN COMPILED since RISC-V 'A' ISA extension is not enabled!\n");
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#endif
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neorv32_uart0_printf("\n\nTests completed.\n");
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return 0;
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}
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/**********************************************************************//**
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* Check results (reference (SW) vs actual hardware).
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*
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* @param[in] num Test case number
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* @param[in] amo_var_old Initial value of atomic variable.
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* @param[in] amo_var_pre Value of atomic variable read from memory (before operation).
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* @param[in] amo_var_new Expected new value of atomic variable.
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* @param[in] amo_var Actual new value of atomic variable.
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* @return zero if results are correct.
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**************************************************************************/
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uint32_t check_result(uint32_t num, uint32_t amo_var_old, uint32_t amo_var_pre, uint32_t amo_var_new, uint32_t amo_var) {
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#if (SILENT_MODE == 0)
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neorv32_uart0_printf("%u: MEM_INITIAL[addr] = 0x%x vs. MEM_PRE[addr] = 0x%x & MEM_NEW_ref[addr] = 0x%x vs. MEM_NEW[addr] = 0x%x, ", num, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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#endif
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if ((amo_var_old != amo_var_pre) || (amo_var_new != amo_var)) {
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#if (SILENT_MODE != 0)
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neorv32_uart0_printf("%u: MEM_INITIAL[addr] = 0x%x vs. MEM_PRE[addr] = 0x%x & MEM_NEW_ref[addr] = 0x%x vs. MEM_NEW[addr] = 0x%x, ", num, amo_var_old, amo_var_pre, amo_var_new, amo_var);
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#endif
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neorv32_uart0_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
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return 1;
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}
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else {
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#if (SILENT_MODE == 0)
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neorv32_uart0_printf("%c[1m[ok]%c[0m\n", 27, 27);
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#endif
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return 0;
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}
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}
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/**********************************************************************//**
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* Print test report.
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*
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* @param[in] num_err Number or errors in this test.
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* @param[in] num_tests Total number of conducted tests.
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**************************************************************************/
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void print_report(int num_err, int num_tests) {
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neorv32_uart0_printf("Errors: %i/%i ", num_err, num_tests);
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if (num_err == 0) {
|
||||
neorv32_uart0_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
||||
}
|
||||
else {
|
||||
neorv32_uart0_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
||||
}
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
# Application makefile.
|
||||
# Use this makefile to configure all relevant CPU / compiler options.
|
||||
|
||||
# Override the default CPU ISA
|
||||
MARCH = rv32ia_zicsr_zifencei
|
||||
|
||||
# Override the default RISC-V GCC prefix
|
||||
#RISCV_PREFIX ?= riscv-none-elf-
|
||||
|
||||
# Override default optimization goal
|
||||
EFFORT = -Os
|
||||
|
||||
# Add extended debug symbols
|
||||
USER_FLAGS += -ggdb -gdwarf-3
|
||||
|
||||
# Adjust processor IMEM size
|
||||
USER_FLAGS += -Wl,--defsym,__neorv32_rom_size=16k
|
||||
|
||||
# Adjust processor DMEM size
|
||||
USER_FLAGS += -Wl,--defsym,__neorv32_ram_size=8k
|
||||
|
||||
# Adjust maximum heap size
|
||||
#USER_FLAGS += -Wl,--defsym,__neorv32_heap_size=1k
|
||||
|
||||
# Additional sources
|
||||
#APP_SRC += $(wildcard ./*.c)
|
||||
#APP_INC += -I .
|
||||
|
||||
# Set path to NEORV32 root directory
|
||||
NEORV32_HOME ?= ../../..
|
||||
|
||||
# Include the main NEORV32 makefile
|
||||
include $(NEORV32_HOME)/sw/common/common.mk
|
||||
|
|
@ -257,7 +257,6 @@ typedef union {
|
|||
|
||||
// CPU core
|
||||
#include "neorv32_cpu.h"
|
||||
#include "neorv32_cpu_amo.h"
|
||||
#include "neorv32_cpu_csr.h"
|
||||
#include "neorv32_cpu_cfu.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,93 +0,0 @@
|
|||
// ================================================================================ //
|
||||
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
|
||||
// Copyright (c) NEORV32 contributors. //
|
||||
// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
|
||||
// Licensed under the BSD-3-Clause license, see LICENSE for details. //
|
||||
// SPDX-License-Identifier: BSD-3-Clause //
|
||||
// ================================================================================ //
|
||||
|
||||
/**
|
||||
* @file neorv32_cpu_amo.h
|
||||
* @brief Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - header file.
|
||||
*
|
||||
* @see https://stnolting.github.io/neorv32/sw/files.html
|
||||
*/
|
||||
|
||||
#ifndef neorv32_cpu_amo_h
|
||||
#define neorv32_cpu_amo_h
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic memory access: load-reservate word.
|
||||
*
|
||||
* @note The address has to be word-aligned - otherwise an alignment exception will be raised.
|
||||
* @warning This function requires the A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr Address (32-bit).
|
||||
* @return Read data word (32-bit).
|
||||
**************************************************************************/
|
||||
inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_amolr(uint32_t addr) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t amo_addr = addr;
|
||||
uint32_t amo_rdata;
|
||||
|
||||
asm volatile ("lr.w %[dst], 0(%[addr])" : [dst] "=r" (amo_rdata) : [addr] "r" (amo_addr));
|
||||
|
||||
return amo_rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic memory access: store-conditional word.
|
||||
*
|
||||
* @note The address has to be word-aligned - otherwise an alignment exception will be raised.
|
||||
* @warning This function requires the A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr Address (32-bit).
|
||||
* @param[in] wdata Data word to-be-written conditionally (32-bit).
|
||||
* @return Status: 0 = ok, 1 = failed (32-bit).
|
||||
**************************************************************************/
|
||||
inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_amosc(uint32_t addr, uint32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t amo_addr = addr;
|
||||
uint32_t amo_wdata = wdata;
|
||||
uint32_t amo_status;
|
||||
|
||||
asm volatile ("sc.w %[dst], %[src], (%[addr])" : [dst] "=r" (amo_status) : [src] "r" (amo_wdata), [addr] "r" (amo_addr));
|
||||
|
||||
return amo_status;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 1; // always fail
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* @name Prototypes
|
||||
**************************************************************************/
|
||||
/**@{*/
|
||||
uint32_t neorv32_cpu_amoswapw(uint32_t addr, uint32_t wdata);
|
||||
uint32_t neorv32_cpu_amoaddw(uint32_t addr, uint32_t wdata);
|
||||
uint32_t neorv32_cpu_amoandw(uint32_t addr, uint32_t wdata);
|
||||
uint32_t neorv32_cpu_amoorw(uint32_t addr, uint32_t wdata);
|
||||
uint32_t neorv32_cpu_amoxorw(uint32_t addr, uint32_t wdata);
|
||||
int32_t neorv32_cpu_amomaxw(uint32_t addr, int32_t wdata);
|
||||
uint32_t neorv32_cpu_amomaxuw(uint32_t addr, uint32_t wdata);
|
||||
int32_t neorv32_cpu_amominw(uint32_t addr, int32_t wdata);
|
||||
uint32_t neorv32_cpu_amominuw(uint32_t addr, uint32_t wdata);
|
||||
/**@}*/
|
||||
|
||||
|
||||
#endif // neorv32_cpu_amo_h
|
||||
|
|
@ -1,338 +0,0 @@
|
|||
// ================================================================================ //
|
||||
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
|
||||
// Copyright (c) NEORV32 contributors. //
|
||||
// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
|
||||
// Licensed under the BSD-3-Clause license, see LICENSE for details. //
|
||||
// SPDX-License-Identifier: BSD-3-Clause //
|
||||
// ================================================================================ //
|
||||
|
||||
/**
|
||||
* @file neorv32_cpu_amo.c
|
||||
* @brief Atomic memory access (read-modify-write) emulation functions using LR/SC pairs - source file.
|
||||
*
|
||||
* @see https://stnolting.github.io/neorv32/sw/files.html
|
||||
*/
|
||||
|
||||
#include <neorv32.h>
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic SWAP (AMOSWAP.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= wdata
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically stored to address (32-bit).
|
||||
* @return Pre-operation data loaded from address (32-bit)
|
||||
**************************************************************************/
|
||||
uint32_t neorv32_cpu_amoswapw(uint32_t addr, uint32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t rdata;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = neorv32_cpu_amolr(addr);
|
||||
status = neorv32_cpu_amosc(addr, wdata);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic ADD (AMOADD.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= MEM[addr] + wdata
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically added to original data at address (32-bit).
|
||||
* @return Pre-operation data loaded from address (32-bit)
|
||||
**************************************************************************/
|
||||
uint32_t neorv32_cpu_amoaddw(uint32_t addr, uint32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t rdata;
|
||||
uint32_t tmp;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = neorv32_cpu_amolr(addr);
|
||||
tmp = rdata + wdata;
|
||||
status = neorv32_cpu_amosc(addr, tmp);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic AND (AMOAND.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= MEM[addr] and wdata
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically AND-ed with original data at address (32-bit).
|
||||
* @return Pre-operation data loaded from address (32-bit)
|
||||
**************************************************************************/
|
||||
uint32_t neorv32_cpu_amoandw(uint32_t addr, uint32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t rdata;
|
||||
uint32_t tmp;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = neorv32_cpu_amolr(addr);
|
||||
tmp = rdata & wdata;
|
||||
status = neorv32_cpu_amosc(addr, tmp);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic OR (AMOOR.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= MEM[addr] or wdata
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically OR-ed with original data at address (32-bit).
|
||||
* @return Pre-operation data loaded from address (32-bit)
|
||||
**************************************************************************/
|
||||
uint32_t neorv32_cpu_amoorw(uint32_t addr, uint32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t rdata;
|
||||
uint32_t tmp;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = neorv32_cpu_amolr(addr);
|
||||
tmp = rdata | wdata;
|
||||
status = neorv32_cpu_amosc(addr, tmp);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic XOR (AMOXOR.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= MEM[addr] xor wdata
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically XOR-ed with original data at address (32-bit).
|
||||
* @return Pre-operation data loaded from address (32-bit)
|
||||
**************************************************************************/
|
||||
uint32_t neorv32_cpu_amoxorw(uint32_t addr, uint32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t rdata;
|
||||
uint32_t tmp;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = neorv32_cpu_amolr(addr);
|
||||
tmp = rdata ^ wdata;
|
||||
status = neorv32_cpu_amosc(addr, tmp);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic signed MAX (AMOMAX.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= maximum_signed(MEM[addr], wdata)
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically MAX-ed with original data at address (signed 32-bit).
|
||||
* @return Pre-operation data loaded from address (signed 32-bit)
|
||||
**************************************************************************/
|
||||
int32_t neorv32_cpu_amomaxw(uint32_t addr, int32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
int32_t rdata;
|
||||
int32_t tmp;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = (int32_t)neorv32_cpu_amolr(addr);
|
||||
tmp = neorv32_aux_max(rdata, wdata);
|
||||
status = neorv32_cpu_amosc(addr, tmp);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic unsigned MAX (AMOMAXU.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= maximum_unsigned(MEM[addr], wdata)
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically MAX-ed with original data at address (unsigned 32-bit).
|
||||
* @return Pre-operation data loaded from address (unsigned 32-bit)
|
||||
**************************************************************************/
|
||||
uint32_t neorv32_cpu_amomaxuw(uint32_t addr, uint32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t rdata;
|
||||
uint32_t tmp;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = (uint32_t)neorv32_cpu_amolr(addr);
|
||||
tmp = neorv32_aux_max(rdata, wdata);
|
||||
status = neorv32_cpu_amosc(addr, tmp);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic signed MIN (AMOMIN.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= minimum_signed(MEM[addr], wdata)
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically MIN-ed with original data at address (signed 32-bit).
|
||||
* @return Pre-operation data loaded from address (signed 32-bit)
|
||||
**************************************************************************/
|
||||
int32_t neorv32_cpu_amominw(uint32_t addr, int32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
int32_t rdata;
|
||||
int32_t tmp;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = (int32_t)neorv32_cpu_amolr(addr);
|
||||
tmp = neorv32_aux_min(rdata, wdata);
|
||||
status = neorv32_cpu_amosc(addr, tmp);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Atomic unsigned MIN (AMOMINU.W).
|
||||
* return <= MEM[addr]; MEM[addr] <= minimum_unsigned(MEM[addr], wdata)
|
||||
*
|
||||
* @note This function requires the CPU A/Zalrsc ISA extension.
|
||||
*
|
||||
* @param[in] addr 32-bit memory address, word-aligned.
|
||||
* @param[in] wdata Data word to be atomically MIN-ed with original data at address (unsigned 32-bit).
|
||||
* @return Pre-operation data loaded from address (unsigned 32-bit)
|
||||
**************************************************************************/
|
||||
uint32_t neorv32_cpu_amominuw(uint32_t addr, uint32_t wdata) {
|
||||
|
||||
#if defined __riscv_atomic
|
||||
uint32_t rdata;
|
||||
uint32_t tmp;
|
||||
uint32_t status;
|
||||
|
||||
while(1) {
|
||||
rdata = (uint32_t)neorv32_cpu_amolr(addr);
|
||||
tmp = neorv32_aux_min(rdata, wdata);
|
||||
status = neorv32_cpu_amosc(addr, tmp);
|
||||
if (status == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return rdata;
|
||||
#else
|
||||
(void)addr;
|
||||
(void)wdata;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue