[docs] minor edits -> "execution safety"

README.md

@@ -41,6 +41,10 @@ The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC
 The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
 custom / customizable microcontroller.
 
+Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
+Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
+are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.
+
 :information_source: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
 
 :books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
@@ -176,8 +180,7 @@ However, the CPU's _front end_ (instruction fetch) and _back end_ (instruction e
 Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
 interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
 It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
-instruction, breakpoint, environment calls). See :books: [_"Full Virtualization"_](https://stnolting.github.io/neorv32/#_full_virtualization)
-for more information.
+instruction, breakpoint, environment calls).
 
 
 ### Available ISA Extensions
@@ -314,6 +317,7 @@ This overview provides some *quick links* to the most important sections of the
 
 * [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the CPU
   * [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
+  * [Full Virtualization](https://stnolting.github.io/neorv32/#_full_virtualization) - hardware execution safety
   * [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
   * [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
   * [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions

docs/datasheet/cpu.adoc

@@ -24,7 +24,8 @@ image::riscv_logo.png[width=350,align=center]
 * Compatible to the RISC-V user specifications and a subset of the RISC-V privileged architecture specifications - passes the official RISC-V Architecture Tests (v2+)
 * Official RISC-V open-source architecture ID
 * Standard RISC-V interrupts (_external_, _timer_, _software_) plus 16 _fast_ interrupts
-* Supports most of the traps from the RISC-V specifications (including bus access exceptions) and traps on all unimplemented/illegal/malformed instructions
+* Supports _all_ of the machine-level traps from the RISC-V specifications (including bus access exceptions and all unimplemented/illegal/malformed instructions)
+** This is a special aspect on _execution safety_ by <<_full_virtualization>>
 * Optional physical memory configuration (PMP), compatible to the RISC-V specifications
 * Optional hardware performance monitors (HPM) for application benchmarking
 * Separated interfaces for instruction fetch and data access (merged into a single processor bus))
@@ -83,6 +84,33 @@ have higher priority). Hence, ALL memory locations including peripheral devices
 address space.
 
 
+// ####################################################################################################################
+:sectnums:
+=== Full Virtualization
+
+Just like the RISC-V ISA the NEORV32 aims to provide _maximum virtualization_ capabilities on CPU _and_ SoC level to
+allow a high standard of **execution safety**. The CPU supports **all** traps specified by the official RISC-V specifications.
+footnote:[If the `Zicsr` CPU extension is enabled (implementing the full set of the privileged architecture).]
+Thus, the CPU provides defined hardware fall-backs via traps for any expected and unexpected situation (e.g. executing an
+malformed instruction word or accessing a not-allocated memory address). For any kind of trap the core is always in a
+defined and fully synchronized state throughout the whole architecture (i.e. there are no out-of-order operations that
+might have to reverted). This allows predictable execution behavior at any time improving overall _execution safety_.
+
+**Execution Safety - NEORV32 Virtualization Features**
+
+* Due to the acknowledged memory accesses the CPU is _always_ sync with the memory system
+(i.e. there is no speculative execution / no out-of-order states).
+* The CPU supports _all_ RISC-V compatible bus exceptions including access exceptions, which are triggered if an
+accessed address does not respond or encounters an internal error during access.
+* Accessed memory addresses (plain memory, but also memory-mapped devices) need to respond within a fixed time
+window. Otherwise a bus access exception is raised.
+* The RISC-V specs. state that executing an malformed instruction results in unpredictable behavior. As an additional
+execution safety feature the NEORV32 CPU ensures that _all_ unimplemented/malformed/illegal instructions do raise an
+illegal instruction exceptions and do not commit any state-changing operation (like writing registers or triggering
+memory operations).
+* To be continued...
+
+
 // ####################################################################################################################
 :sectnums:
 === RISC-V Compatibility
@@ -762,36 +790,9 @@ The presented values of the *floating-point execution cycles* are average values
 instructions (using pure-software libraries) is ~17..140 times higher.
 
 
-
-// ####################################################################################################################
-include::cpu_csr.adoc[]
-
-
-
 <<<
 // ####################################################################################################################
-:sectnums:
-==== Full Virtualization
-
-Just like the RISC-V ISA the NEORV32 aims to support _ maximum virtualization_ capabilities
-on CPU _and_ SoC level. The CPU supports **all** traps specified by the official RISC-V specifications.footnote:[If the `Zicsr` CPU
-extension is enabled (implementing the full set of the privileged architecture).]
-Thus, the CPU provides defined hardware fall-backs for any expected and unexpected situation (e.g. executing an
-malformed instruction word or accessing a not-allocated address). For any kind of trap the core is always in a
-defined and fully synchronized state throughout the whole architecture (i.e. there are no out-of-order operations that
-have to be made undone). This allows predictable execution behavior - and thus, defined operations to resolve the cause
-of the trap - at any time improving overall _execution safety_.
-
-**NEORV32-Specific Virtualization Features**
-
-* Due to the acknowledged memory accesses the CPU is _always_ sync with the memory system
-(i.e. there is no speculative execution / no out-of-order states).
-* The CPU supports _all_ RISC-V bus exceptions including access exceptions that are triggered if an
-accessed address does not respond or encounters an internal error during access.
-* The RISC-V specs. state that executing an malformed instruction results in unpredictable behavior. As an additional security feature,
-the NEORV32 CPU ensures that _all_ unimplemented/malformed/illegal instructions _do raise an illegal instruction trap_ and
-_do not commit any operation_ (like writing registers or triggering memory operations).
-* To be continued...
+include::cpu_csr.adoc[]
 
 
 <<<

docs/datasheet/overview.adoc

@@ -10,6 +10,10 @@ timers, serial interfaces, general purpose IO ports and an external bus interfac
 memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb
 compatible on-chip debugger accessible via JTAG.
 
+Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
+Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
+are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.
+
 The software framework of the processor comes with application makefiles, software libraries for all CPU
 and processor features, a bootloader, a runtime environment and several example programs - including a port
 of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as