[docs] replace MTIME by CLINT

README.md

@@ -152,7 +152,7 @@ allows booting application code via UART or from external SPI flash
 
 **Timers and Counters**
 
-* 64-bit machine timer ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
+* core local interruptor ([CLINT](https://stnolting.github.io/neorv32/#_core_local_interruptor_clint)), RISC-V-compatible
 * 32-bit general purpose timer ([GPTMR](https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr))
 * watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))
 

docs/datasheet/cpu.adoc

@@ -39,7 +39,8 @@ instruction exception (see section  <<_full_virtualization>>).
 .`time[h]` CSRs (Wall Clock Time)
 [IMPORTANT]
 The NEORV32 does not implement the `time[h]` registers. Any access to these registers will trap. It is
-recommended that the trap handler software provides a means of accessing the platform-defined <<_machine_system_timer_mtime>>.
+recommended that the trap handler software provides a means of accessing the the machine timer of the
+<<_core_local_interruptor_clint>>.
 
 .No Hardware Support of Misaligned Memory Accesses
 [IMPORTANT]
@@ -777,7 +778,7 @@ counter CSRs. Section <<_machine_counter_and_timer_csrs>> shows a list of all `Z
 .Time CSRs
 [NOTE]
 The user-mode `time[h]` CSRs are **not implemented**. Any access will trap allowing the trap handler to
-retrieve system time from the <<_machine_system_timer_mtime>>.
+retrieve system time from the <<_core_local_interruptor_clint>>.
 
 .Mandatory Extension
 [NOTE]
@@ -1327,8 +1328,8 @@ written to the according CSRs when a trap is triggered:
 | `TRAP_CODE_S_ACCESS`     | bus timeout, bus access error or <<_smpmp_isa_extension,PMP>> rule violation during store data operation
 | `TRAP_CODE_FIRQ_*`       | caused by interrupt-condition of **processor-internal modules**, see <<_neorv32_specific_fast_interrupt_requests>>
 | `TRAP_CODE_MEI`          | machine external interrupt (via dedicated <<_processor_top_entity_signals>>)
-| `TRAP_CODE_MSI`          | machine software interrupt (via dedicated <<_processor_top_entity_signals>>)
-| `TRAP_CODE_MTI`          | machine timer interrupt (internal <<_machine_system_timer_mtime>> or via dedicated <<_processor_top_entity_signals>>)
+| `TRAP_CODE_MSI`          | machine software interrupt (internal <<_core_local_interruptor_clint>> or via dedicated <<_processor_top_entity_signals>>)
+| `TRAP_CODE_MTI`          | machine timer interrupt (internal <<_core_local_interruptor_clint>> or via dedicated <<_processor_top_entity_signals>>)
 |=======================
 
 .Resumable Exceptions

docs/datasheet/cpu_csr.adoc

@@ -254,8 +254,8 @@ Machine-mode software can discover available `Z*` _sub-extensions_ (like `Zicsr`
 [options="header",grid="rows"]
 |=======================
 | Bit   | Name [C] | R/W | Function
-| 3     | `CSR_MIE_MSIE` | r/w | **MSIE**: Machine _software_ interrupt enable
-| 7     | `CSR_MIE_MTIE` | r/w | **MTIE**: Machine _timer_ interrupt enable (from <<_machine_system_timer_mtime>>)
+| 3     | `CSR_MIE_MSIE` | r/w | **MSIE**: Machine _software_ interrupt enable (from <<_core_local_interruptor_clint>>)
+| 7     | `CSR_MIE_MTIE` | r/w | **MTIE**: Machine _timer_ interrupt enable (from <<_core_local_interruptor_clint>>)
 | 11    | `CSR_MIE_MEIE` | r/w | **MEIE**: Machine _external_ interrupt enable
 | 31:16 | `CSR_MIE_FIRQ15E` : `CSR_MIE_FIRQ0E` | r/w | Fast interrupt channel 15..0 enable
 |=======================
@@ -436,8 +436,8 @@ However, any write-access will be ignored and will not cause an exception to mai
 |=======================
 | Bit | Name [C] | R/W | Function
 | 3     | `CSR_MIP_MSIP`                       | r/- | **MSIP**: Machine _software_ interrupt pending, triggered by `msi_i` top port (see <<_cpu_top_entity_signals>>); _cleared by source-specific mechanism_
-| 7     | `CSR_MIP_MTIP`                       | r/- | **MTIP**: Machine _timer_ interrupt pending, triggered by `mei_i` top port (see <<_cpu_top_entity_signals>>); _cleared by source-specific mechanism_
-| 11    | `CSR_MIP_MEIP`                       | r/- | **MEIP**: Machine _external_ interrupt pending, triggered by `mti_i` top port (see <<_cpu_top_entity_signals>>) or by the processor-internal <<_machine_system_timer_mtime>>; _cleared by source-specific mechanism_
+| 7     | `CSR_MIP_MTIP`                       | r/- | **MTIP**: Machine _timer_ interrupt pending, triggered by `mei_i` top port (see <<_cpu_top_entity_signals>>)or by the processor-internal <<(from <<_core_local_interruptor_clint>>)>>; _cleared by source-specific mechanism_
+| 11    | `CSR_MIP_MEIP`                       | r/- | **MEIP**: Machine _external_ interrupt pending, triggered by `mti_i` top port (see <<_cpu_top_entity_signals>>) or by the processor-internal <<(from <<_core_local_interruptor_clint>>)>>; _cleared by source-specific mechanism_
 | 31:16 | `CSR_MIP_FIRQ15P` : `CSR_MIP_FIRQ0P` | r/- | **FIRQxP**: Fast interrupt channel 15..0 pending, see <<_neorv32_specific_fast_interrupt_requests>>; _cleared by source-specific mechanism_
 |=======================
 
@@ -625,7 +625,8 @@ implementation of the according modes.
 .`time[h]` CSRs (Wall Clock Time)
 [IMPORTANT]
 The NEORV32 does not implement the user-mode `time[h]` registers. Any access to these registers will trap.
-It is recommended that the trap handler software provides a means of accessing the platform-defined <<_machine_system_timer_mtime>>.
+It is recommended that the trap handler software provides a means of accessing the machine timer oft the
+<<_core_local_interruptor_clint>>.
 
 .Instruction Retired Counter Increment
 [NOTE]

docs/datasheet/overview.adoc

@@ -203,6 +203,7 @@ neorv32_top.vhd                 - NEORV32 PROCESSOR/SOC TOP ENTITY
 ├neorv32_bus.vhd                - SoC bus infrastructure modules
 ├neorv32_cache.vhd              - Generic cache module
 ├neorv32_cfs.vhd                - Custom functions subsystem
+├neorv32_clint.vhd              - Core local interruptor
 ├neorv32_clockgate.vhd          - Generic clock gating switch
 ├neorv32_crc.vhd                - Cyclic redundancy check unit
 ├neorv32_debug_dm.vhd           - on-chip debugger: debug module
@@ -215,7 +216,6 @@ neorv32_top.vhd                 - NEORV32 PROCESSOR/SOC TOP ENTITY
 ├neorv32_gptmr.vhd              - General purpose 32-bit timer
 ├neorv32_imem.vhd               - Generic processor-internal instruction memory
 │└neorv32_application_image.vhd - IMEM application initialization image (package)
-├neorv32_mtime.vhd              - Machine system timer
 ├neorv32_neoled.vhd             - NeoPixel (TM) compatible smart LED interface
 ├neorv32_onewire.vhd            - One-Wire serial interface controller
 ├neorv32_package.vhd            - Main VHDL package file
@@ -384,7 +384,7 @@ https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configur
 | IO Switch         | _SoC bus infrastructure_                                       | 217 |   0 |        0 |    0
 | iCACHE            | Instruction cache (2x4 blocks, 64 bytes per block)             | 458 | 296 |     4096 |    0
 | IMEM              | Processor-internal instruction memory (16kB)                   |   7 |   2 |   131072 |    0
-| MTIME             | Machine system timer                                           | 307 | 166 |        0 |    0
+| CLINT             | Core local interruptor                                         | 307 | 166 |        0 |    0
 | NEOLED            | Smart LED Interface (NeoPixel/WS28128) (FIFO_depth=1)          | 171 | 129 |        0 |    0
 | ONEWIRE           | 1-wire interface                                               | 105 |  77 |        0 |    0
 | PWM               | Pulse_width modulation controller (4 channels)                 |  91 |  81 |        0 |    0

docs/datasheet/soc.adoc

@@ -23,7 +23,7 @@ image::neorv32_processor.png[align=center]
 * _optional_ caches (<<_processor_internal_instruction_cache_icache,**I-CACHE**>>, <<_processor_internal_data_cache_dcache,**D-CACHE**>>,
 <<_execute_in_place_module_xip,**XIP-CACHE**>>, <<_processor_external_bus_interface_xbus,**XBUS-CACHE**>>)
 * _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
-* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
+* _optional_ RISC-V-compatible core local interruptor (<<_core_local_interruptor_clint,**CLINT**>>)
 * _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>,
 <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS)
 * _optional_ serial peripheral interface host controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
@@ -162,8 +162,8 @@ to all inputs and output so the synthesis tool can insert an explicit IO (bounda
 | `cfs_out_o`      | 32 | out |   -   | custom CFS output signal conduit
 5+^| **<<_smart_led_interface_neoled>>**
 | `neoled_o`       |  1 | out |   -   | asynchronous serial data output
-5+^| **<<_machine_system_timer_mtime>>**
-| `mtime_time_o`   | 64 | out |   -   | MTIME system time output
+5+^| **<<_core_local_interruptor_clint>**
+| `mtime_time_o`   | 64 | out |   -   | CLINT.MTIMER system time output
 5+^| **<<_external_interrupt_controller_xirq>>**
 | `xirq_i`         | 32 |  in | `'L'` | external interrupt requests
 5+^| **RISC-V Machine-Mode <<_processor_interrupts>>**
@@ -286,7 +286,7 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 4+^| **Peripheral/IO Modules**
 | `IO_DISABLE_SYSINFO`    | boolean   | false         | Disable <<_system_configuration_information_memory_sysinfo>> module; ⚠️ not recommended - for advanced users only!
 | `IO_GPIO_NUM`           | natural   | 0             | Number of general purpose input/output pairs of the <<_general_purpose_input_and_output_port_gpio>>.
-| `IO_MTIME_EN`           | boolean   | false         | Implement the <<_machine_system_timer_mtime>>.
+| `IO_CLINT_EN`           | boolean   | false         | Implement the <<_core_local_interruptor_clint>>.
 | `IO_UART0_EN`           | boolean   | false         | Implement the <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>>.
 | `IO_UART0_RX_FIFO`      | natural   | 1             | UART0 RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
 | `IO_UART0_TX_FIFO`      | natural   | 1             | UART0 TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
@@ -421,8 +421,8 @@ specifications. However, bare-metal system can also repurpose these interrupts.
 [options="header",grid="rows"]
 |=======================
 | Top signal | Description
-| `mtime_irq_i` | Machine timer interrupt from _processor-external_ MTIME unit (`MTI`). This IRQ is only available if the processor-internal <<_machine_system_timer_mtime>> unit is not implemented.
-| `msw_irq_i`   | Machine software interrupt (`MSI`). This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
+| `mtime_irq_i` | Machine timer interrupt from _processor-external_ CLINT (`MTI`). This IRQ is only available if the processor-internal <<_core_local_interruptor_clint>> unit is not implemented.
+| `msw_irq_i`   | Machine software interrupt from _processor-external_ CLINT (`MSI`). This IRQ is only available if the processor-internal <<_core_local_interruptor_clint>> unit is not implemented.
 | `mext_irq_i`  | Machine external interrupt (`MEI`). This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
 |=======================
 
@@ -777,7 +777,7 @@ include::soc_crc.adoc[]
 
 include::soc_wdt.adoc[]
 
-include::soc_mtime.adoc[]
+include::soc_clint.adoc[]
 
 include::soc_uart.adoc[]
 

docs/datasheet/software.adoc

@@ -75,7 +75,7 @@ The NEORV32 HAL consists of the following files.
 | `neorv32_gptmr.c`   | `neorv32_gptmr.h`      | <<_general_purpose_timer_gptmr>> HAL
 | -                   | `neorv32_intrinsics.h` | Macros for intrinsics and custom instructions
 | -                   | `neorv32_legacy.h`     | Legacy compatibility layer / wrappers (**do not use for new designs**)
-| `neorv32_mtime.c`   | `neorv32_mtime.h`      | <<_machine_system_timer_mtime>> HAL
+| `neorv32_clint.c`   | `neorv32_clint.h`      | <<_core_local_interruptor_clint>> HAL
 | `neorv32_neoled.c`  | `neorv32_neoled.h`     | <<_smart_led_interface_neoled>> HAL
 | `neorv32_onewire.c` | `neorv32_onewire.h`    | <<_one_wire_serial_interface_controller_onewire>> HAL
 | `neorv32_pwm.c`     | `neorv32_pwm.h`        | <<_pulse_width_modulation_controller_pwm>> HAL

docs/datasheet/software_bootloader.adoc

@@ -38,7 +38,7 @@ The bootloader requires certain CPU and SoC extensions and modules to be enabled
 | **REQUIRED**  | At least 512 bytes of data memory (processor-internal DMEM or processor-external DMEM) are required for the bootloader's stack and global variables.
 | _RECOMMENDED_ | For user interaction via the <<_bootloader_console>> (like uploading executables) the primary UART (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0>>) is required.
 | _RECOMMENDED_ | The default bootloader uses bit 0 of the <<_general_purpose_input_and_output_port_gpio>> output port to drive a high-active "heart beat" status LED.
-| _RECOMMENDED_ | The <<_machine_system_timer_mtime>> is used to control blinking of the status LED and also to automatically trigger the <<_auto_boot_sequence>>.
+| _RECOMMENDED_ | The machine timer of the <<_core_local_interruptor_clint>> is used to control blinking of the status LED and also to automatically trigger the <<_auto_boot_sequence>>.
 | OPTIONAL      | The SPI controller (<<_serial_peripheral_interface_controller_spi>>) is needed to store/load executable from external flash using the <<_auto_boot_sequence>>.
 | OPTIONAL      | The XIP controller (<<_execute_in_place_module_xip>>) is needed to boot/execute code directly from a pre-programmed SPI flash.
 |=======================

docs/datasheet/software_rte.adoc

@@ -121,13 +121,13 @@ Do **NOT** use the `((interrupt))` attribute for the application trap handler fu
 will place a `mret` instruction to the end of it making it impossible to return to the first-level
 trap handler of the RTE core, which will cause stack corruption.
 
-The following example shows how to install a custom handler (`custom_mtime_irq_handler`) for handling
-the RISC-V machine timer (MTIME) interrupt:
+The following example shows how to install a custom handler (`custom_timer_irq_handler`) for handling
+the RISC-V CLINT timer interrupt:
 
-.Installing a MTIME IRQ Handler
+.Installing a CLINT Timer IRQ Handler
 [source,c]
 ----
-neorv32_rte_handler_install(RTE_TRAP_MTI, custom_mtime_irq_handler);
+neorv32_rte_handler_install(RTE_TRAP_MTI, custom_timer_irq_handler);
 ----
 
 User-defined trap handlers can also be un-installed. This will remove the users trap handler from the RTE core
@@ -140,10 +140,10 @@ int neorv32_rte_handler_uninstall(uint8_t id);
 ----
 
 The argument `id` defines the identifier of the according trap that shall be un-installed. 
-The following example shows how to un-install the custom handler `custom_mtime_irq_handler` from the
-RISC-V machine timer (MTIME) interrupt:
+The following example shows how to un-install the custom handler `custom_timer_irq_handler` from the
+RISC-V CLINT timer interrupt:
 
-.Example: Removing the Custom MTIME IRQ Handler
+.Example: Removing the Custom CLINT Timer IRQ Handler
 [source,c]
 ----
 neorv32_rte_handler_uninstall(RTE_TRAP_MTI);

docs/userguide/simulating_the_processor.adoc

@@ -100,7 +100,7 @@ Blinking LED demo program
 Makefile targets:
 
 * `clean_all`: delete all artifacts and rebuild everything
-* `install`: install executable 
+* `install`: install executable
 * `sim`: run GHDL simulation
 
 .Adjusting the Testbench Configuration
@@ -131,7 +131,7 @@ Installing application image to ../../../rtl/core/neorv32_application_image.vhd
 Simulating processor using default testbench...
 GHDL simulation run parameters: --stop-time=10ms <4>
 ../rtl/core/neorv32_top.vhd:351:5:@0ms:(assertion note): [NEORV32] The NEORV32 RISC-V Processor (v1.10.7.6), github.com/stnolting/neorv32
-../rtl/core/neorv32_top.vhd:357:5:@0ms:(assertion note): [NEORV32] Processor Configuration: CPU IMEM-ROM DMEM I-CACHE D-CACHE XBUS XBUS-CACHE XIP XIP-CACHE GPIO MTIME UART0 UART1 SPI SDI TWI TWD PWM WDT TRNG CFS NEOLED XIRQ GPTMR ONEWIRE DMA SLINK CRC SYSINFO OCD-AUTH
+../rtl/core/neorv32_top.vhd:357:5:@0ms:(assertion note): [NEORV32] Processor Configuration: CPU IMEM-ROM DMEM I-CACHE D-CACHE XBUS XBUS-CACHE XIP XIP-CACHE CLINT GPIO UART0 UART1 SPI SDI TWI TWD PWM WDT TRNG CFS NEOLED XIRQ GPTMR ONEWIRE DMA SLINK CRC SYSINFO OCD-AUTH
 ../rtl/core/neorv32_top.vhd:411:5:@0ms:(assertion note): [NEORV32] BOOT_MODE_SELECT = 2: booting IMEM image
 ../rtl/core/neorv32_clockgate.vhd:38:3:@0ms:(assertion warning): [NEORV32] Clock gating enabled (using default/generic clock switch).
 ../rtl/core/neorv32_cpu.vhd:135:3:@0ms:(assertion note): [NEORV32] CPU ISA: rv32ibmux_zalrsc_zba_zbb_zbkb_zbkc_zbkx_zbs_zicntr_zicond_zicsr_zifencei_zihpm_zfinx_zkn_zknd_zkne_zknh_zks_zksed_zksh_zkt_zmmul_zxcfu_sdext_sdtrig_smpmp

rtl/test_setups/README.md

@@ -33,7 +33,7 @@ your FPGA/board.
 
 This setup configures a `rv32imc_Zicsr_Zicntr` CPU with 16kB IMEM (as pre-initialized ROM),
 8kB DMEM and includes the **GPIO** module to drive 8 external signals (`gpio_o`)
-and the **MTIME** module for generating timer interrupts.
+and the **CLINT** module for generating timer interrupts.
 The setup uses the ["direct boot"](https://stnolting.github.io/neorv32/#_direct_boot)
 configuration, so software applications are "installed" directly into the
 processor-internal IMEM (via the bitstream) during synthesis.
@@ -45,7 +45,7 @@ processor-internal IMEM (via the bitstream) during synthesis.
 ### > [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/test_setups/neorv32_test_setup_bootloader.vhd)
 
 This setup configures a `rv32imc_Zicsr_Zicntr` CPU with 16kB IMEM (as RAM), 8kB DMEM
-and includes the **GPIO** module to drive 8 external signals (`gpio_o`), the **MTIME**
+and includes the **GPIO** module to drive 8 external signals (`gpio_o`), the **CLINT**
 module for generating timer interrupts and **UART0** to interface with the bootloader or application
 (via `uart0_txd_o` and `uart0_rxd_i`) via a serial terminal.
 The setup uses the ["indirect boot"](https://stnolting.github.io/neorv32/#_indirect_boot)
@@ -59,7 +59,7 @@ and a serial terminal.
 ### > [`neorv32_test_setup_on_chip_debugger.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd)
 
 This setup configures a `rv32imc_Zicsr_Zicntr_Zifencei` CPU with 16kB IMEM (as RAM), 8kB DMEM
-and includes the **GPIO** module to drive 8 external signals (`gpio_o`), the **MTIME**
+and includes the **GPIO** module to drive 8 external signals (`gpio_o`), the **CLINT**
 module for generating timer interrupts, **UART0** to interface with the bootloader or application
 (via `uart0_txd_o` and `uart0_rxd_i`) via a serial terminal and also the RISC-V-compatible
 on-chip debugger (**OCD**), which is accessible via a standard JTAG interface (`jtag_*`).

sw/example/dhrystone/README.md

@@ -19,7 +19,7 @@ Executable (neorv32_exe.bin) size in bytes:
 ```
 
 The default number of iterations is 10000. You can modify this by adding `USER_FLAGS+=-DDHRY_ITERS=2000000` to the makefile invocation.
-Dhrystone will require an IMEM size of at least 8kB and a DMEM size of about 11kB. The MTIME machine timer is used for timing benchmarking.
+Dhrystone will require an IMEM size of at least 8kB and a DMEM size of about 11kB. The CLINT machine timer is used for time benchmarking.
 Note that the Drhystone score is normalized to the original VAX machine (SiFive is giving a nice overview
 about this at https://www.sifive.com/blog/dhrystone-performance-tuning-on-the-freedom-platform):