[docs] minor edits

README.md

@@ -84,7 +84,7 @@ The processor passes the official RISC-V architecture tests to ensure compatibil
 [neorv32-riscof](https://github.com/stnolting/neorv32-riscof) repository. It can successfully run _any_ C program
 (for example from the [`sw/example`](https://github.com/stnolting/neorv32/tree/main/sw/example) folder) including CoreMark
 and FreeRTOS and can be synthesized for _any_ target technology - [tested](https://github.com/stnolting/neorv32-setups)
-on Intel, AMD and Lattice FPGAs. The conversion into a single, plain-Verilog module file is automatically checked by the
+on Intel, AMD, Cologne Chip and Lattice FPGAs. The conversion into a single, plain-Verilog module file is automatically checked by the
 [neorv32-verilog](https://github.com/stnolting/neorv32-verilog) repository.
 
 

docs/legal.adoc

@@ -62,6 +62,7 @@ OF THE POSSIBILITY OF SUCH DAMAGE.
 * "ModelSim" is a trademark of Mentor Graphics – A Siemens Business.
 * "Quartus Prime" and "Cyclone" are trademarks of Intel Corporation.
 * "iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
+* "GateMate" is a trademark of Cologne Chip AG.
 * "Windows" is a trademark of Microsoft Corporation.
 * "Tera Term" copyright by T. Teranishi.
 * "NeoPixel" is a trademark of Adafruit Industries.

docs/userguide/application_program_compilation.adoc

@@ -5,11 +5,6 @@
 This guide shows how to compile an example C-code application into a NEORV32 executable that
 can be uploaded via the bootloader or the on-chip debugger.
 
-[IMPORTANT]
-If your FPGA board does not provide such an interface - don't worry!
-Section <<_installing_an_executable_directly_into_memory>> shows how to
-run custom programs on your FPGA setup without having a UART.
-
 [start=1]
 . Open a terminal console and navigate to one of the project's example programs. For instance, navigate to the
 simple `sw/example_demo_blink_led` example program. This program uses the NEORV32 GPIO module to display