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https://github.com/stnolting/neorv32.git
synced 2025-04-23 21:57:33 -04:00
[sw] cleanup clint.mtimecmp calls
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parent
635e6d2626
commit
bc4c63864b
3 changed files with 16 additions and 16 deletions
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@ -483,7 +483,7 @@ void __attribute__((interrupt("machine"))) bootloader_trap_handler(void) {
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#endif
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// set time for next IRQ
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if (neorv32_clint_available()) {
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neorv32_clint_mtimecmp_set(0, neorv32_clint_time_get() + (NEORV32_SYSINFO->CLK/4));
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neorv32_clint_mtimecmp_set(neorv32_clint_time_get() + (NEORV32_SYSINFO->CLK/4));
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}
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}
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@ -70,7 +70,7 @@ int main() {
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neorv32_uart0_printf("Unix timestamp: %u\n", (uint32_t)neorv32_clint_unixtime_get);
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// configure MTIME timer to not trigger
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neorv32_clint_mtimecmp_set(0, -1);
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neorv32_clint_mtimecmp_set(-1);
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// install CLINT handlers to RTE
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neorv32_rte_handler_install(RTE_TRAP_MTI, mti_irq_handler);
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@ -80,7 +80,7 @@ int main() {
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neorv32_uart0_printf("\nStarting real-time clock demo...\n");
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// configure MTIME timer's first interrupt to trigger after 1 second starting from now
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neorv32_clint_mtimecmp_set(0, neorv32_clint_time_get() + neorv32_sysinfo_get_clk());
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neorv32_clint_mtimecmp_set(neorv32_clint_time_get() + neorv32_sysinfo_get_clk());
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// enable machine time and software interrupts
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neorv32_cpu_csr_set(CSR_MIE, (1 << CSR_MIE_MTIE) + (1 << CSR_MIE_MSIE));
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@ -104,13 +104,13 @@ int main() {
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void mti_irq_handler(void) {
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// configure MTIME timer's next interrupt to trigger after 1 second starting from now
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neorv32_clint_mtimecmp_set(0, neorv32_clint_mtimecmp_get(0) + neorv32_sysinfo_get_clk());
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neorv32_clint_mtimecmp_set(neorv32_clint_mtimecmp_get() + neorv32_sysinfo_get_clk());
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// toggle output port bit 0
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neorv32_gpio_pin_toggle(0);
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// trigger software interrupt (just for fun)
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neorv32_clint_msi_set(0);
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// trigger software interrupt for this core (just for fun)
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neorv32_clint_msi_set(neorv32_cpu_csr_read(CSR_MHARTID));
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// show date in human-readable format
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date_t date;
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@ -127,8 +127,8 @@ void mti_irq_handler(void) {
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**************************************************************************/
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void msi_irq_handler(void) {
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// clear machine software interrupt
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NEORV32_CLINT->MSWI[0] = 0;
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// clear machine software interrupt for this core
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neorv32_clint_msi_clr(neorv32_cpu_csr_read(CSR_MHARTID));
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neorv32_uart0_printf("\n[Machine Software Interrupt!]\n");
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}
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@ -139,7 +139,7 @@ int main() {
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}
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// set CMP of CLINT MTIMER to max to prevent an IRQ
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neorv32_clint_mtimecmp_set(0, -1);
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neorv32_clint_mtimecmp_set(-1);
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neorv32_clint_time_set(0);
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// get number of implemented PMP regions
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@ -787,7 +787,7 @@ int main() {
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cnt_test++;
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// configure MTIMER (and check overflow from low word to high word)
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neorv32_clint_mtimecmp_set(0, 0x0000000100000000ULL);
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neorv32_clint_mtimecmp_set(0x0000000100000000ULL);
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neorv32_clint_time_set(0x00000000FFFFFFFEULL);
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// enable interrupt
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neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE);
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@ -808,7 +808,7 @@ int main() {
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}
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// no more MTIME interrupts
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neorv32_clint_mtimecmp_set(0, -1);
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neorv32_clint_mtimecmp_set(-1);
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}
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else {
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PRINT_STANDARD("[n.a.]\n");
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@ -894,7 +894,7 @@ int main() {
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// fire CLINT.MTIMER IRQ
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neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE);
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neorv32_clint_mtimecmp_set(0, 0); // force interrupt
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neorv32_clint_mtimecmp_set(0); // force interrupt
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volatile int test_cnt = 0;
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@ -929,7 +929,7 @@ int main() {
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neorv32_cpu_csr_write(CSR_MIE, 0);
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// fire CLINT.MTIMER IRQ
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neorv32_clint_mtimecmp_set(0, 0); // force interrupt
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neorv32_clint_mtimecmp_set(0); // force interrupt
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// wait some time for the IRQ to arrive the CPU
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asm volatile ("nop");
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@ -938,7 +938,7 @@ int main() {
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uint32_t was_pending = neorv32_cpu_csr_read(CSR_MIP) & (1 << CSR_MIP_MTIP); // should be pending now
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// clear pending MTI
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neorv32_clint_mtimecmp_set(0, -1);
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neorv32_clint_mtimecmp_set(-1);
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uint32_t is_pending = neorv32_cpu_csr_read(CSR_MIP) & (1 << CSR_MIP_MTIP); // should NOT be pending anymore
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@ -1770,7 +1770,7 @@ int main() {
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cnt_test++;
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// program wake-up timer
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neorv32_clint_mtimecmp_set(0, neorv32_clint_time_get() + 300);
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neorv32_clint_mtimecmp_set(neorv32_clint_time_get() + 300);
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// enable CLINT.MTIMER interrupt
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neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE);
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@ -1812,7 +1812,7 @@ int main() {
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neorv32_cpu_csr_clr(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE);
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// program wake-up timer
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neorv32_clint_mtimecmp_set(0, neorv32_clint_time_get() + 300);
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neorv32_clint_mtimecmp_set(neorv32_clint_time_get() + 300);
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// enable machine timer interrupt
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neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE);
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