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[ocd-firmware] use minimal ISA config

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stnolting 2025-01-10 20:35:59 +01:00
parent 9aab53898a
commit c1ae45b2e8
2 changed files with 11 additions and 11 deletions
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4
sw/ocd-firmware/makefile
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@ -1,7 +1,7 @@
override APP_SRC = park_loop.S
override MARCH = rv32i_zicsr_zifencei
override MARCH = rv32e_zicsr_zifencei
override MABI = ilp32e
override LD_SCRIPT = ./debug_rom.ld
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../..
include $(NEORV32_HOME)/sw/common/common.mk

18
sw/ocd-firmware/park_loop.S
View file

@ -1,11 +1,9 @@
// ================================================================================ //
// NEORV32 CPU - park_loop.S - Execution-Based On-Chip Debugger (OCD) Firmware //
// -------------------------------------------------------------------------------- //
// WARNING! This code only supports up to 4 harts! //
// -------------------------------------------------------------------------------- //
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
// Copyright (c) NEORV32 contributors. //
// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //
// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
// Licensed under the BSD-3-Clause license, see LICENSE for details. //
// SPDX-License-Identifier: BSD-3-Clause //
// ================================================================================ //
@ -18,6 +16,8 @@
.global entry_exception
.global entry_park
// [NOTE] compile this code with minimal ISA configuration: rv32e_zicsr_zifencei
// debug module (DM) address map
.equ DM_CODE_BASE, 0xFFFFFE00 // base address of code ROM (park loop)
.equ DM_PBUF_BASE, 0xFFFFFE80 // base address of program buffer
@ -46,34 +46,34 @@ entry_exception:
// BASE + 16: normal entry - halt CPU: ebreak in debug-mode, halt request or return from single-stepped instruction
entry_park:
csrw dscratch0, x8 // backup x8 to dscratch0 so we have a GPR available
csrr x8, mhartid // get hart ID (0..3)
csrr x8, mhartid // get hart ID
sw x8, (DM_SREG_BASE+ACK_HLT)(zero) // send halt-acknowledge
// polling loop - waiting for requests
park_loop:
csrr x8, mhartid // get hart ID (0..3)
csrr x8, mhartid // get hart ID
lbu x8, DM_SREG_BASE(x8) // read hart-specific byte from request register
andi x8, x8, 1 << REQ_EXE // execute-request bit set?
bnez x8, execute
csrr x8, mhartid // get hart ID (0..3)
csrr x8, mhartid // get hart ID
lbu x8, DM_SREG_BASE(x8) // read hart-specific byte from request register
andi x8, x8, 1 << REQ_RES // resume-request bit set?
beqz x8, park_loop
// resume normal operation
resume:
csrr x8, mhartid // get hart ID (0..3)
csrr x8, mhartid // get hart ID
sw x8, (DM_SREG_BASE+ACK_RES)(zero) // send resume-acknowledge
csrr x8, dscratch0 // restore x8 from dscratch0
dret // exit debug mode
// execute program buffer (implicit ebreak at the end of the buffer will bring us back to "entry_park")
execute:
csrr x8, mhartid // get hart ID (0..3)
csrr x8, mhartid // get hart ID
sw x8, (DM_SREG_BASE+ACK_EXE)(zero) // send execute-acknowledge
csrr x8, dscratch0 // restore x8 from dscratch0
fence.i // synchronize instruction fetch with memory (PBUF)
fence.i // synchronize instruction fetch with memory-mapped PBUF
jalr zero, zero, %lo(DM_PBUF_BASE) // jump to beginning of program buffer (PBUF)
// fill remaining ROM space with instructions that cause a debug-mode-internal exception