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fixed bug in crt0.S dummy trap handler

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This commit is contained in:
stnolting 2020-07-25 10:10:03 +02:00
parent 491ea7fcc1
commit c1c4e47e7e
2 changed files with 26 additions and 9 deletions
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30
sw/common/bootloader_crt0.S
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@ -102,26 +102,42 @@ __crt0_the_end:
// *********************************************************
// dummy trap handler (for exceptions & IRQs)
// bootloader has to be compiled without any CPU extensions
// - especially without C extension!
// tries to move on to next instruction
// *********************************************************
.balign 4
.global __crt0_dummy_trap_handler
.balign 4
__crt0_dummy_trap_handler:
addi sp, sp, -4
addi sp, sp, -8
sw x8, 0(sp)
sw x9, 4(sp)
csrr x8, mcause
blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt
__crt0_dummy_trap_handler_compute_return:
csrr x8, mepc
addi x8, x8, +4 // move on to next instruction if exception
// is compressed instruction?
lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
addi x8, x8, +2 // only this for compressed instructions
csrw mepc, x8 // set return address when compressed instruction
addi x8, zero, 3
bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
// is uncompressed instruction
csrr x8, mepc
addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions
csrw mepc, x8
__crt0_dummy_trap_handler_irq:
lw x8, 0(sp)
addi sp, sp, +4
lw x9, 0(sp)
lw x8, 4(sp)
addi sp, sp, +8
mret

5
sw/common/crt0.S
View file

@ -208,7 +208,8 @@ __crt0_this_is_the_end_end:
// dummy trap handler (for exceptions & IRQs)
// tries to move on to next instruction
// *********************************************************
.balign 4
.global __crt0_dummy_trap_handler
.balign 4
__crt0_dummy_trap_handler:
addi sp, sp, -8
@ -223,7 +224,7 @@ __crt0_dummy_trap_handler_compute_return:
// is compressed instruction?
lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
andi x9, zero, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
addi x8, x8, +2 // only this for compressed instructions
csrw mepc, x8 // set return address when compressed instruction