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[sw/example/cpu_test] minor edits

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stnolting 2020-12-23 18:55:24 +01:00
parent 005b496916
commit c4ccf78655
1 changed files with 42 additions and 38 deletions
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80
sw/example/cpu_test/main.c
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@ -305,7 +305,6 @@ int main() {
// wait some time to have a nice increment
asm volatile ("nop");
asm volatile ("nop");
asm volatile ("nop");
// make sure cycle counter has incremented and there was no exception during access
if ((neorv32_cpu_get_cycle() > cycle_csr_test) &&
@ -337,7 +336,6 @@ int main() {
// wait some time to have a nice increment
asm volatile ("nop");
asm volatile ("nop");
asm volatile ("nop");
// make sure instruction counter has incremented and there was no exception during access
if ((neorv32_cpu_get_instret() > instret_csr_test) &&
@ -560,7 +558,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
// no more mtime interrupts
neorv32_mtime_set_timecmp(-1);
@ -599,7 +596,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
// no more mtime interrupts
neorv32_mtime_set_timecmp(-1);
@ -886,10 +882,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MTI) {
test_ok();
@ -921,10 +913,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MSI) {
test_ok();
@ -953,10 +941,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MEI) {
test_ok();
@ -987,10 +971,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_0) {
test_ok();
@ -1030,10 +1010,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_1) {
test_ok();
@ -1087,10 +1063,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
@ -1130,10 +1102,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
test_ok();
@ -1170,10 +1138,6 @@ int main() {
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
test_ok();
@ -1438,9 +1402,10 @@ int main() {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (succeeding access): ", cnt_test);
#ifdef __riscv_atomic
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
// skip if A-mode is implemented
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
cnt_test++;
@ -1463,6 +1428,9 @@ int main() {
else {
neorv32_uart_printf("skipped (on real hardware)\n");
}
#else
neorv32_uart_printf("skipped (not implemented)\n");
#endif
// ----------------------------------------------------------
@ -1471,9 +1439,10 @@ int main() {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (failing access): ", cnt_test);
#ifdef __riscv_atomic
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
// skip if A-mode is implemented
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
cnt_test++;
@ -1495,6 +1464,41 @@ int main() {
else {
neorv32_uart_printf("skipped (on real hardware)\n");
}
#else
neorv32_uart_printf("skipped (not implemented)\n");
#endif
// ----------------------------------------------------------
// Test AMO atomic operation - should raise illegal instruction exception
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Atomic AMOSWAP test (should raise illegal CMD exception): ", cnt_test);
#ifdef __riscv_atomic
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
cnt_test++;
// AMO operations are not implemented!
// this should cause an illegal instruction exception
asm volatile ("amoswap.w x0, x0, (x0)");
// atomic compare-and-swap
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
#else
neorv32_uart_printf("skipped (not implemented)\n");
#endif
// ----------------------------------------------------------