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[docs] SDI: edit max clock speed

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stnolting 2025-04-07 22:43:01 +02:00
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docs/datasheet/soc_sdi.adoc
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@ -66,7 +66,7 @@ yet. However, experiments have shown that the SDI module can also deal with both
All SDI operations are clocked by the external `sdi_clk_i` signal. This signal is synchronized to the processor's
clock domain to simplify timing behavior. This clock synchronization requires the external SDI clock
(`sdi_clk_i`) does **not exceed 1/4 of the processor's main clock**.
(`sdi_clk_i`) to not **not exceed 1/4 of the processor's main clock**.
**SDI Interrupt**