github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 06:07:52 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

remove Wishbone tag signal

Browse source
This commit is contained in:
stnolting 2022-06-28 17:54:32 +02:00
parent 79210d809e
commit c68059a369
1 changed files with 1 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

3
rtl/system_integration/neorv32_litex_core_complex.vhd
View file

@ -80,7 +80,6 @@ entity neorv32_litex_core_complex is
jtag_tms_i : in std_ulogic; -- mode select
-- Wishbone bus interface --
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
@ -197,7 +196,7 @@ begin
jtag_tdo_o => jtag_tdo_o, -- serial data output
jtag_tms_i => jtag_tms_i, -- mode select
-- Wishbone bus interface --
wb_tag_o => wb_tag_o, -- request tag
wb_tag_o => open, -- request tag
wb_adr_o => wb_adr_o, -- address
wb_dat_i => wb_dat_i, -- read data
wb_dat_o => wb_dat_o, -- write data