github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 14:17:51 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[top] add scalar crypto ISA extension generics

Browse source
This commit is contained in:
stnolting 2024-09-25 00:15:31 +02:00
parent b884034433
commit c8db86b741
2 changed files with 12 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
docs/datasheet/soc.adoc
View file

@ -211,11 +211,15 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
| `CPU_EXTENSION_RISCV_E` | boolean | false | Enable <<_e_isa_extension>> (reduced register file size).
| `CPU_EXTENSION_RISCV_M` | boolean | false | Enable <<_m_isa_extension>> (hardware-based integer multiplication and division).
| `CPU_EXTENSION_RISCV_U` | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode).
| CPU_EXTENSION_RISCV_Zbkx` | boolean | false | Enable <<_zbkx_isa_extension>> (scalar cryptography crossbar permutations).
| `CPU_EXTENSION_RISCV_Zfinx` | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit).
| `CPU_EXTENSION_RISCV_Zicntr` | boolean | true | Enable <<_zicntr_isa_extension>> (CPU base counters).
| `CPU_EXTENSION_RISCV_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional operations).
| `CPU_EXTENSION_RISCV_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors).
| `CPU_EXTENSION_RISCV_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
| CPU_EXTENSION_RISCV_Zknd` | boolean | false | Enable <<_Zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
| CPU_EXTENSION_RISCV_Zkne` | boolean | false | Enable <<_Zkne_isa_extension>> (scalar cryptography NIST AES encryption instructions).
| CPU_EXTENSION_RISCV_Zknh` | boolean | false | Enable <<_Zknh_isa_extension>> (scalar cryptography NIST hash instructions).
| `CPU_EXTENSION_RISCV_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).
4+^| **CPU <<_architecture>> Tuning Options**
| `FAST_MUL_EN` | boolean | false | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.

8
rtl/core/neorv32_top.vhd
View file

@ -39,10 +39,14 @@ entity neorv32_top is
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkx : boolean := false; -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
CPU_EXTENSION_RISCV_Zicond : boolean := false; -- implement integer conditional operations?
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
CPU_EXTENSION_RISCV_Zknd : boolean := false; -- implement cryptography NIST AES decryption extension?
CPU_EXTENSION_RISCV_Zkne : boolean := false; -- implement cryptography NIST AES encryption extension?
CPU_EXTENSION_RISCV_Zknh : boolean := false; -- implement cryptography NIST hash extension?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
@ -449,10 +453,14 @@ begin
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E,
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M,
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U,
CPU_EXTENSION_RISCV_Zbkx => CPU_EXTENSION_RISCV_Zbkx,
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx,
CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,
CPU_EXTENSION_RISCV_Zicond => CPU_EXTENSION_RISCV_Zicond,
CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm,
CPU_EXTENSION_RISCV_Zknd => CPU_EXTENSION_RISCV_Zknd,
CPU_EXTENSION_RISCV_Zkne => CPU_EXTENSION_RISCV_Zkne,
CPU_EXTENSION_RISCV_Zknh => CPU_EXTENSION_RISCV_Zknh,
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul,
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu,
CPU_EXTENSION_RISCV_Sdext => ON_CHIP_DEBUGGER_EN,