mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-24 14:17:51 -04:00
[misa,mxisa] remove A, add Zalrsc
This commit is contained in:
stnolting
parent
1562f5c94f
commit
ca6628e46e
4 changed files with 15 additions and 17 deletions
|
|
@ -220,7 +220,6 @@ will _not_ cause an illegal instruction exception.
|
|||
[options="header",grid="rows"]
|
||||
|=======================
|
||||
| Bit | Name [C] | R/W | Function
|
||||
| 0 | `CSR_MISA_A_EXT` | r/- | **A**: CPU extension (atomic memory access) available, set when <<_a_isa_extension>> enabled
|
||||
| 1 | `CSR_MISA_B_EXT` | r/- | **B**: CPU extension (bit-manipulation) available, set when <<_b_isa_extension>> enabled
|
||||
| 2 | `CSR_MISA_C_EXT` | r/- | **C**: CPU extension (compressed instruction) available, set when <<_c_isa_extension>> enabled
|
||||
| 4 | `CSR_MISA_E_EXT` | r/- | **E**: CPU extension (embedded) available, set when <<_e_isa_extension>> enabled
|
||||
|
|
@ -972,7 +971,8 @@ discover ISA sub-extensions and CPU configuration options
|
|||
| 22 | `CSR_MXISA_ZBA` | r/- | <<_zba_isa_extension>> available
|
||||
| 23 | `CSR_MXISA_ZBB` | r/- | <<_zbb_isa_extension>> available
|
||||
| 24 | `CSR_MXISA_ZBS` | r/- | <<_zbs_isa_extension>> available
|
||||
| 27:25 | - | r/- | _reserved_, hardwired to zero
|
||||
| 25 | `CSR_MXISA_ZALRSC` | r/- | <<_zalrsc_isa_extension>> available
|
||||
| 27:26 | - | r/- | _reserved_, hardwired to zero
|
||||
| 28 | `CSR_MXISA_RFHWRST` | r/- | full hardware reset of register file available when set (`REGFILE_HW_RST`)
|
||||
| 29 | `CSR_MXISA_FASTMUL` | r/- | fast multiplication available when set (`FAST_MUL_EN`)
|
||||
| 30 | `CSR_MXISA_FASTSHIFT` | r/- | fast shifts available when set (`FAST_SHIFT_EN`)
|
||||
|
|
|
|||
|
|
@ -35,17 +35,17 @@ entity neorv32_cpu_control is
|
|||
DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug-mode parking loop entry address, 4-byte aligned
|
||||
DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug-mode exception entry address, 4-byte aligned
|
||||
-- RISC-V ISA Extensions --
|
||||
RISCV_ISA_A : boolean; -- implement atomic memory operations extension
|
||||
RISCV_ISA_B : boolean; -- implement bit-manipulation extension
|
||||
RISCV_ISA_C : boolean; -- implement compressed extension
|
||||
RISCV_ISA_E : boolean; -- implement embedded-class register file extension
|
||||
RISCV_ISA_M : boolean; -- implement mul/div extension
|
||||
RISCV_ISA_U : boolean; -- implement user mode extension
|
||||
RISCV_ISA_Zalrsc : boolean; -- implement atomic reservation-set extension
|
||||
RISCV_ISA_Zba : boolean; -- implement shifted-add bit-manipulation extension
|
||||
RISCV_ISA_Zbb : boolean; -- implement basic bit-manipulation extension
|
||||
RISCV_ISA_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography
|
||||
RISCV_ISA_Zbkc : boolean; -- implement carry-less multiplication instructions
|
||||
RISCV_ISA_Zbkx : boolean; -- implement cryptography crossbar permutation extension?
|
||||
RISCV_ISA_Zbkx : boolean; -- implement cryptography crossbar permutation extension
|
||||
RISCV_ISA_Zbs : boolean; -- implement single-bit bit-manipulation extension
|
||||
RISCV_ISA_Zfinx : boolean; -- implement 32-bit floating-point extension
|
||||
RISCV_ISA_Zicntr : boolean; -- implement base counters
|
||||
|
|
@ -525,7 +525,7 @@ begin
|
|||
when opcode_jal_c => -- J-immediate
|
||||
alu_imm_o <= replicate_f(execute_engine.ir(31), 12) & execute_engine.ir(19 downto 12) & execute_engine.ir(20) & execute_engine.ir(30 downto 21) & '0';
|
||||
when opcode_amo_c => -- atomic memory access
|
||||
if RISCV_ISA_A then alu_imm_o <= (others => '0'); end if;
|
||||
if RISCV_ISA_Zalrsc then alu_imm_o <= (others => '0'); end if;
|
||||
when others =>
|
||||
NULL; -- use default
|
||||
end case;
|
||||
|
|
@ -684,7 +684,7 @@ begin
|
|||
end case;
|
||||
|
||||
-- memory read/write access --
|
||||
if RISCV_ISA_A and (opcode(2) = opcode_amo_c(2)) then -- atomic lr/sc
|
||||
if RISCV_ISA_Zalrsc and (opcode(2) = opcode_amo_c(2)) then -- atomic lr/sc
|
||||
ctrl_nxt.lsu_rw <= execute_engine.ir(instr_funct7_lsb_c+2);
|
||||
else -- normal load/store
|
||||
ctrl_nxt.lsu_rw <= execute_engine.ir(5);
|
||||
|
|
@ -850,7 +850,7 @@ begin
|
|||
(trap_ctrl.exc_buf(exc_saccess_c) = '1') or (trap_ctrl.exc_buf(exc_laccess_c) = '1') or -- access exception
|
||||
(trap_ctrl.exc_buf(exc_salign_c) = '1') or (trap_ctrl.exc_buf(exc_lalign_c) = '1') or -- alignment exception
|
||||
(trap_ctrl.exc_buf(exc_illegal_c) = '1') then -- illegal instruction exception
|
||||
if (RISCV_ISA_A and (opcode(2) = opcode_amo_c(2))) or (opcode(5) = '0') then -- atomic operation / normal load
|
||||
if (RISCV_ISA_Zalrsc and (opcode(2) = opcode_amo_c(2))) or (opcode(5) = '0') then -- atomic operation / normal load
|
||||
ctrl_nxt.rf_wb_en <= '1'; -- allow write-back to register file (won't happen in case of exception)
|
||||
end if;
|
||||
execute_engine.state_nxt <= DISPATCH;
|
||||
|
|
@ -1077,8 +1077,8 @@ begin
|
|||
end case;
|
||||
|
||||
when opcode_amo_c => -- atomic memory operation (LR/SC)
|
||||
if RISCV_ISA_A and (execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") and
|
||||
(execute_engine.ir(instr_funct7_lsb_c+6 downto instr_funct7_lsb_c+3) = "0001") then -- LR.W/SC.W
|
||||
if RISCV_ISA_Zalrsc and (execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") and
|
||||
(execute_engine.ir(instr_funct7_lsb_c+6 downto instr_funct7_lsb_c+3) = "0001") then -- LR.W/SC.W
|
||||
illegal_cmd <= '0';
|
||||
else
|
||||
illegal_cmd <= '1';
|
||||
|
|
@ -1722,7 +1722,6 @@ begin
|
|||
-- when csr_mstatush_c => csr.rdata <= (others => '0'); -- machine status register, high word - hardwired to zero
|
||||
|
||||
when csr_misa_c => -- ISA and extensions
|
||||
csr.rdata(0) <= bool_to_ulogic_f(RISCV_ISA_A); -- A CPU extension
|
||||
csr.rdata(1) <= bool_to_ulogic_f(RISCV_ISA_B); -- B CPU extension
|
||||
csr.rdata(2) <= bool_to_ulogic_f(RISCV_ISA_C); -- C CPU extension
|
||||
csr.rdata(4) <= bool_to_ulogic_f(RISCV_ISA_E); -- E CPU extension
|
||||
|
|
@ -1911,8 +1910,8 @@ begin
|
|||
csr.rdata(22) <= bool_to_ulogic_f(RISCV_ISA_Zba); -- Zba: shifted-add bit-manipulation
|
||||
csr.rdata(23) <= bool_to_ulogic_f(RISCV_ISA_Zbb); -- Zbb: basic bit-manipulation extension
|
||||
csr.rdata(24) <= bool_to_ulogic_f(RISCV_ISA_Zbs); -- Zbs: single-bit bit-manipulation extension
|
||||
csr.rdata(25) <= bool_to_ulogic_f(RISCV_ISA_Zalrsc); -- Zalrsc: reservation set extension
|
||||
-- reserved --
|
||||
csr.rdata(25) <= '0';
|
||||
csr.rdata(26) <= '0';
|
||||
csr.rdata(27) <= '0';
|
||||
-- tuning options --
|
||||
|
|
|
|||
|
|
@ -287,12 +287,9 @@ enum NEORV32_CSR_MIP_enum {
|
|||
* CPU misa CSR (r/-): Machine instruction set extensions
|
||||
**************************************************************************/
|
||||
enum NEORV32_CSR_MISA_enum {
|
||||
CSR_MISA_A = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/
|
||||
CSR_MISA_B = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/
|
||||
CSR_MISA_C = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
|
||||
CSR_MISA_D = 3, /**< CPU misa CSR (3): D: Double-precision floating-point extension available (r/-)*/
|
||||
CSR_MISA_E = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */
|
||||
CSR_MISA_F = 5, /**< CPU misa CSR (5): F: Single-precision floating-point extension available (r/-)*/
|
||||
CSR_MISA_I = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
|
||||
CSR_MISA_M = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
|
||||
CSR_MISA_U = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
|
||||
|
|
@ -329,9 +326,10 @@ enum NEORV32_CSR_XISA_enum {
|
|||
CSR_MXISA_ZKSH = 19, /**< CPU mxisa CSR (19): scalar cryptography - ShangMi hash functions (r/-)*/
|
||||
CSR_MXISA_ZKSED = 20, /**< CPU mxisa CSR (20): scalar cryptography - ShangMi block cyphers (r/-)*/
|
||||
CSR_MXISA_ZKS = 21, /**< CPU mxisa CSR (21): scalar cryptography - ShangMi algorithm suite (r/-)*/
|
||||
CSR_MXISA_ZBA = 22, /**< CPU mxisa CSR (22): shifted-add bit-manipulation operation (r/-)*/
|
||||
CSR_MXISA_ZBB = 23, /**< CPU mxisa CSR (23): basic bit-manipulation operation (r/-)*/
|
||||
CSR_MXISA_ZBS = 24, /**< CPU mxisa CSR (24): single-bit bit-manipulation operation (r/-)*/
|
||||
CSR_MXISA_ZBA = 22, /**< CPU mxisa CSR (22): shifted-add bit-manipulation operations (r/-)*/
|
||||
CSR_MXISA_ZBB = 23, /**< CPU mxisa CSR (23): basic bit-manipulation operations (r/-)*/
|
||||
CSR_MXISA_ZBS = 24, /**< CPU mxisa CSR (24): single-bit bit-manipulation operations (r/-)*/
|
||||
CSR_MXISA_ZALRSC = 25, /**< CPU mxisa CSR (25): atomic reservation-set operations (r/-)*/
|
||||
// Tuning options
|
||||
CSR_MXISA_RFHWRST = 28, /**< CPU mxisa CSR (28): register file has full hardware reset (r/-)*/
|
||||
CSR_MXISA_FASTMUL = 29, /**< CPU mxisa CSR (29): DSP-based multiplication (M extensions only) (r/-)*/
|
||||
|
|
|
|||
|
|
@ -450,6 +450,7 @@ void neorv32_rte_print_hw_config(void) {
|
|||
if (tmp & (1<<CSR_MXISA_SDEXT)) { neorv32_uart0_printf("Sdext "); }
|
||||
if (tmp & (1<<CSR_MXISA_SDTRIG)) { neorv32_uart0_printf("Sdtrig "); }
|
||||
if (tmp & (1<<CSR_MXISA_SMPMP)) { neorv32_uart0_printf("Smpmp "); }
|
||||
if (tmp & (1<<CSR_MXISA_ZALRSC)) { neorv32_uart0_printf("Zalrsc "); }
|
||||
if (tmp & (1<<CSR_MXISA_ZBA)) { neorv32_uart0_printf("Zba "); }
|
||||
if (tmp & (1<<CSR_MXISA_ZBB)) { neorv32_uart0_printf("Zbb "); }
|
||||
if (tmp & (1<<CSR_MXISA_ZBKB)) { neorv32_uart0_printf("Zbkb "); }
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue