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https://github.com/stnolting/neorv32.git
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[top] add IO_HWSPINLOCK_EN generic
connect new hardware module and assign base address
This commit is contained in:
stnolting
parent
a3c6584faa
commit
ce911560fb
3 changed files with 144 additions and 120 deletions
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@ -29,7 +29,7 @@ package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110202"; -- hardware version
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110203"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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constant XLEN : natural := 32; -- native data path width
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@ -57,39 +57,39 @@ package neorv32_package is
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constant mem_uncached_begin_c : std_ulogic_vector(31 downto 0) := x"f0000000";
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-- IO Address Map (base address must be aligned to the region's size) --
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constant iodev_size_c : natural := 64*1024; -- size of a single IO device (bytes)
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constant base_io_bootrom_c : std_ulogic_vector(31 downto 0) := x"ffe00000";
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe10000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe20000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe30000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe40000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe50000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe60000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe70000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe80000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe90000"; -- reserved
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constant base_io_twd_c : std_ulogic_vector(31 downto 0) := x"ffea0000";
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constant base_io_cfs_c : std_ulogic_vector(31 downto 0) := x"ffeb0000";
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constant base_io_slink_c : std_ulogic_vector(31 downto 0) := x"ffec0000";
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constant base_io_dma_c : std_ulogic_vector(31 downto 0) := x"ffed0000";
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constant base_io_crc_c : std_ulogic_vector(31 downto 0) := x"ffee0000";
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffef0000"; -- reserved
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constant base_io_pwm_c : std_ulogic_vector(31 downto 0) := x"fff00000";
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constant base_io_gptmr_c : std_ulogic_vector(31 downto 0) := x"fff10000";
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constant base_io_onewire_c : std_ulogic_vector(31 downto 0) := x"fff20000";
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"fff30000"; -- reserved
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constant base_io_clint_c : std_ulogic_vector(31 downto 0) := x"fff40000";
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constant base_io_uart0_c : std_ulogic_vector(31 downto 0) := x"fff50000";
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constant base_io_uart1_c : std_ulogic_vector(31 downto 0) := x"fff60000";
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constant base_io_sdi_c : std_ulogic_vector(31 downto 0) := x"fff70000";
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constant base_io_spi_c : std_ulogic_vector(31 downto 0) := x"fff80000";
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constant base_io_twi_c : std_ulogic_vector(31 downto 0) := x"fff90000";
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constant base_io_trng_c : std_ulogic_vector(31 downto 0) := x"fffa0000";
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constant base_io_wdt_c : std_ulogic_vector(31 downto 0) := x"fffb0000";
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constant base_io_gpio_c : std_ulogic_vector(31 downto 0) := x"fffc0000";
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constant base_io_neoled_c : std_ulogic_vector(31 downto 0) := x"fffd0000";
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constant base_io_sysinfo_c : std_ulogic_vector(31 downto 0) := x"fffe0000";
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constant base_io_ocd_c : std_ulogic_vector(31 downto 0) := x"ffff0000";
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constant iodev_size_c : natural := 64*1024; -- size of a single IO device (bytes)
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constant base_io_bootrom_c : std_ulogic_vector(31 downto 0) := x"ffe00000";
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe10000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe20000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe30000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe40000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe50000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe60000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe70000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe80000"; -- reserved
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe90000"; -- reserved
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constant base_io_twd_c : std_ulogic_vector(31 downto 0) := x"ffea0000";
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constant base_io_cfs_c : std_ulogic_vector(31 downto 0) := x"ffeb0000";
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constant base_io_slink_c : std_ulogic_vector(31 downto 0) := x"ffec0000";
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constant base_io_dma_c : std_ulogic_vector(31 downto 0) := x"ffed0000";
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constant base_io_crc_c : std_ulogic_vector(31 downto 0) := x"ffee0000";
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--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffef0000"; -- reserved
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constant base_io_pwm_c : std_ulogic_vector(31 downto 0) := x"fff00000";
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constant base_io_gptmr_c : std_ulogic_vector(31 downto 0) := x"fff10000";
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constant base_io_onewire_c : std_ulogic_vector(31 downto 0) := x"fff20000";
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constant base_io_hwspinlock_c : std_ulogic_vector(31 downto 0) := x"fff30000";
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constant base_io_clint_c : std_ulogic_vector(31 downto 0) := x"fff40000";
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constant base_io_uart0_c : std_ulogic_vector(31 downto 0) := x"fff50000";
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constant base_io_uart1_c : std_ulogic_vector(31 downto 0) := x"fff60000";
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constant base_io_sdi_c : std_ulogic_vector(31 downto 0) := x"fff70000";
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constant base_io_spi_c : std_ulogic_vector(31 downto 0) := x"fff80000";
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constant base_io_twi_c : std_ulogic_vector(31 downto 0) := x"fff90000";
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constant base_io_trng_c : std_ulogic_vector(31 downto 0) := x"fffa0000";
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constant base_io_wdt_c : std_ulogic_vector(31 downto 0) := x"fffb0000";
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constant base_io_gpio_c : std_ulogic_vector(31 downto 0) := x"fffc0000";
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constant base_io_neoled_c : std_ulogic_vector(31 downto 0) := x"fffd0000";
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constant base_io_sysinfo_c : std_ulogic_vector(31 downto 0) := x"fffe0000";
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constant base_io_ocd_c : std_ulogic_vector(31 downto 0) := x"ffff0000";
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-- On-Chip Debugger - Debug Module Entry Points (Code ROM) --
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constant dm_exc_entry_c : std_ulogic_vector(31 downto 0) := x"fffffe00"; -- = base_io_ocd_c + code_rom_base + 0
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@ -891,7 +891,8 @@ package neorv32_package is
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IO_SLINK_EN : boolean := false;
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IO_SLINK_RX_FIFO : natural range 1 to 2**15 := 1;
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IO_SLINK_TX_FIFO : natural range 1 to 2**15 := 1;
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IO_CRC_EN : boolean := false
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IO_CRC_EN : boolean := false;
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IO_HWSPINLOCK_EN : boolean := false
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);
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port (
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-- Global control --
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@ -95,7 +95,7 @@ entity neorv32_top is
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DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
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-- External bus interface (XBUS) --
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XBUS_EN : boolean := false; -- implement external memory bus interface?
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XBUS_EN : boolean := false; -- implement external memory bus interface
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XBUS_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
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XBUS_REGSTAGE_EN : boolean := false; -- add XBUS register stage
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XBUS_CACHE_EN : boolean := false; -- enable external bus cache (x-cache)
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@ -105,40 +105,41 @@ entity neorv32_top is
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-- Processor peripherals --
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IO_DISABLE_SYSINFO : boolean := false; -- disable the SYSINFO module (for advanced users only)
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IO_GPIO_NUM : natural range 0 to 32 := 0; -- number of GPIO input/output pairs (0..32)
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IO_CLINT_EN : boolean := false; -- implement core local interruptor (CLINT)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_CLINT_EN : boolean := false; -- implement core local interruptor (CLINT)
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)
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IO_UART0_RX_FIFO : natural range 1 to 2**15 := 1; -- RX FIFO depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO : natural range 1 to 2**15 := 1; -- TX FIFO depth, has to be a power of two, min 1
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)
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IO_UART1_RX_FIFO : natural range 1 to 2**15 := 1; -- RX FIFO depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO : natural range 1 to 2**15 := 1; -- TX FIFO depth, has to be a power of two, min 1
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)
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IO_SPI_FIFO : natural range 1 to 2**15 := 1; -- RTX FIFO depth, has to be a power of two, min 1
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IO_SDI_EN : boolean := false; -- implement serial data interface (SDI)?
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IO_SDI_EN : boolean := false; -- implement serial data interface (SDI)
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IO_SDI_FIFO : natural range 1 to 2**15 := 1; -- RTX FIFO depth, has to be zero or a power of two, min 1
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)
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IO_TWI_FIFO : natural range 1 to 2**15 := 1; -- RTX FIFO depth, has to be zero or a power of two, min 1
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IO_TWD_EN : boolean := false; -- implement two-wire device (TWD)?
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IO_TWD_EN : boolean := false; -- implement two-wire device (TWD)
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IO_TWD_RX_FIFO : natural range 1 to 2**15 := 1; -- TX FIFO depth, has to be zero or a power of two, min 1
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IO_TWD_TX_FIFO : natural range 1 to 2**15 := 1; -- RX FIFO depth, has to be zero or a power of two, min 1
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IO_PWM_NUM_CH : natural range 0 to 16 := 0; -- number of PWM channels to implement (0..16)
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)
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IO_TRNG_FIFO : natural range 1 to 2**15 := 1; -- data FIFO depth, has to be a power of two, min 1
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_IN_SIZE : natural := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : natural := 32; -- size of CFS output conduit in bits
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IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)
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IO_NEOLED_TX_FIFO : natural range 1 to 2**15 := 1; -- NEOLED FIFO depth, has to be a power of two, min 1
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IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
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IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)?
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IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)
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IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)
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IO_ONEWIRE_FIFO : natural range 1 to 2**15 := 1; -- RTX FIFO depth, has to be zero or a power of two, min 1
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IO_DMA_EN : boolean := false; -- implement direct memory access controller (DMA)?
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IO_SLINK_EN : boolean := false; -- implement stream link interface (SLINK)?
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IO_DMA_EN : boolean := false; -- implement direct memory access controller (DMA)
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IO_SLINK_EN : boolean := false; -- implement stream link interface (SLINK)
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IO_SLINK_RX_FIFO : natural range 1 to 2**15 := 1; -- RX FIFO depth, has to be a power of two, min 1
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IO_SLINK_TX_FIFO : natural range 1 to 2**15 := 1; -- TX FIFO depth, has to be a power of two, min 1
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IO_CRC_EN : boolean := false -- implement cyclic redundancy check unit (CRC)?
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IO_CRC_EN : boolean := false; -- implement cyclic redundancy check unit (CRC)
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IO_HWSPINLOCK_EN : boolean := false -- implement hardware spinlocks (HWSPINLOCK)
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);
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port (
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-- Global control --
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@ -311,7 +312,7 @@ architecture neorv32_top_rtl of neorv32_top is
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type io_devices_enum_t is (
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IODEV_BOOTROM, IODEV_OCD, IODEV_SYSINFO, IODEV_NEOLED, IODEV_GPIO, IODEV_WDT, IODEV_TRNG,
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IODEV_TWI, IODEV_SPI, IODEV_SDI, IODEV_UART1, IODEV_UART0, IODEV_CLINT, IODEV_ONEWIRE,
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IODEV_GPTMR, IODEV_PWM, IODEV_CRC, IODEV_DMA, IODEV_SLINK, IODEV_CFS, IODEV_TWD
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IODEV_GPTMR, IODEV_PWM, IODEV_CRC, IODEV_DMA, IODEV_SLINK, IODEV_CFS, IODEV_HWSPINLOCK, IODEV_TWD
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);
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type iodev_req_t is array (io_devices_enum_t) of bus_req_t;
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type iodev_rsp_t is array (io_devices_enum_t) of bus_rsp_t;
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@ -377,6 +378,7 @@ begin
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cond_sel_string_f(IO_ONEWIRE_EN, "ONEWIRE ", "") &
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cond_sel_string_f(IO_DMA_EN, "DMA ", "") &
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cond_sel_string_f(IO_SLINK_EN, "SLINK ", "") &
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cond_sel_string_f(IO_HWSPINLOCK_EN, "HWSPINLOCK ", "") &
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cond_sel_string_f(IO_CRC_EN, "CRC ", "") &
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cond_sel_string_f(io_sysinfo_en_c, "SYSINFO ", "") &
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cond_sel_string_f(OCD_EN, cond_sel_string_f(OCD_AUTHENTICATION, "OCD-AUTH ", "OCD "), "") &
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@ -642,7 +644,7 @@ begin
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end generate; -- /core_complex
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-- Inter-Core Communication (ICC) Links ---------------------------------------------------
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-- Inter-Core Communication (ICC) Links - Cross-Connect -----------------------------------
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-- -------------------------------------------------------------------------------------------
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icc_connect: process(icc_tx)
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begin
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@ -966,76 +968,76 @@ begin
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INREG_EN => true,
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OUTREG_EN => true,
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DEV_SIZE => iodev_size_c,
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DEV_00_EN => bootrom_en_c, DEV_00_BASE => base_io_bootrom_c,
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DEV_01_EN => false, DEV_01_BASE => (others => '0'), -- reserved
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DEV_02_EN => false, DEV_02_BASE => (others => '0'), -- reserved
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DEV_03_EN => false, DEV_03_BASE => (others => '0'), -- reserved
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DEV_04_EN => false, DEV_04_BASE => (others => '0'), -- reserved
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DEV_05_EN => false, DEV_05_BASE => (others => '0'), -- reserved
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DEV_06_EN => false, DEV_06_BASE => (others => '0'), -- reserved
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DEV_07_EN => false, DEV_07_BASE => (others => '0'), -- reserved
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DEV_08_EN => false, DEV_08_BASE => (others => '0'), -- reserved
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DEV_09_EN => false, DEV_09_BASE => (others => '0'), -- reserved
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DEV_10_EN => IO_TWD_EN, DEV_10_BASE => base_io_twd_c,
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DEV_11_EN => IO_CFS_EN, DEV_11_BASE => base_io_cfs_c,
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DEV_12_EN => IO_SLINK_EN, DEV_12_BASE => base_io_slink_c,
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DEV_13_EN => IO_DMA_EN, DEV_13_BASE => base_io_dma_c,
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DEV_14_EN => IO_CRC_EN, DEV_14_BASE => base_io_crc_c,
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DEV_15_EN => false, DEV_15_BASE => (others => '0'), -- reserved
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DEV_16_EN => io_pwm_en_c, DEV_16_BASE => base_io_pwm_c,
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DEV_17_EN => IO_GPTMR_EN, DEV_17_BASE => base_io_gptmr_c,
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DEV_18_EN => IO_ONEWIRE_EN, DEV_18_BASE => base_io_onewire_c,
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DEV_19_EN => false, DEV_19_BASE => (others => '0'), -- reserved
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DEV_20_EN => IO_CLINT_EN, DEV_20_BASE => base_io_clint_c,
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DEV_21_EN => IO_UART0_EN, DEV_21_BASE => base_io_uart0_c,
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DEV_22_EN => IO_UART1_EN, DEV_22_BASE => base_io_uart1_c,
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DEV_23_EN => IO_SDI_EN, DEV_23_BASE => base_io_sdi_c,
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DEV_24_EN => IO_SPI_EN, DEV_24_BASE => base_io_spi_c,
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DEV_25_EN => IO_TWI_EN, DEV_25_BASE => base_io_twi_c,
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DEV_26_EN => IO_TRNG_EN, DEV_26_BASE => base_io_trng_c,
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DEV_27_EN => IO_WDT_EN, DEV_27_BASE => base_io_wdt_c,
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DEV_28_EN => io_gpio_en_c, DEV_28_BASE => base_io_gpio_c,
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DEV_29_EN => IO_NEOLED_EN, DEV_29_BASE => base_io_neoled_c,
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DEV_30_EN => io_sysinfo_en_c, DEV_30_BASE => base_io_sysinfo_c,
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DEV_31_EN => OCD_EN, DEV_31_BASE => base_io_ocd_c
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DEV_00_EN => bootrom_en_c, DEV_00_BASE => base_io_bootrom_c,
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DEV_01_EN => false, DEV_01_BASE => (others => '0'), -- reserved
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DEV_02_EN => false, DEV_02_BASE => (others => '0'), -- reserved
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DEV_03_EN => false, DEV_03_BASE => (others => '0'), -- reserved
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DEV_04_EN => false, DEV_04_BASE => (others => '0'), -- reserved
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DEV_05_EN => false, DEV_05_BASE => (others => '0'), -- reserved
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DEV_06_EN => false, DEV_06_BASE => (others => '0'), -- reserved
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DEV_07_EN => false, DEV_07_BASE => (others => '0'), -- reserved
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DEV_08_EN => false, DEV_08_BASE => (others => '0'), -- reserved
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DEV_09_EN => false, DEV_09_BASE => (others => '0'), -- reserved
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DEV_10_EN => IO_TWD_EN, DEV_10_BASE => base_io_twd_c,
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DEV_11_EN => IO_CFS_EN, DEV_11_BASE => base_io_cfs_c,
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DEV_12_EN => IO_SLINK_EN, DEV_12_BASE => base_io_slink_c,
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DEV_13_EN => IO_DMA_EN, DEV_13_BASE => base_io_dma_c,
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DEV_14_EN => IO_CRC_EN, DEV_14_BASE => base_io_crc_c,
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DEV_15_EN => false, DEV_15_BASE => (others => '0'), -- reserved
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DEV_16_EN => io_pwm_en_c, DEV_16_BASE => base_io_pwm_c,
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DEV_17_EN => IO_GPTMR_EN, DEV_17_BASE => base_io_gptmr_c,
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DEV_18_EN => IO_ONEWIRE_EN, DEV_18_BASE => base_io_onewire_c,
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DEV_19_EN => IO_HWSPINLOCK_EN, DEV_19_BASE => base_io_hwspinlock_c,
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DEV_20_EN => IO_CLINT_EN, DEV_20_BASE => base_io_clint_c,
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DEV_21_EN => IO_UART0_EN, DEV_21_BASE => base_io_uart0_c,
|
||||
DEV_22_EN => IO_UART1_EN, DEV_22_BASE => base_io_uart1_c,
|
||||
DEV_23_EN => IO_SDI_EN, DEV_23_BASE => base_io_sdi_c,
|
||||
DEV_24_EN => IO_SPI_EN, DEV_24_BASE => base_io_spi_c,
|
||||
DEV_25_EN => IO_TWI_EN, DEV_25_BASE => base_io_twi_c,
|
||||
DEV_26_EN => IO_TRNG_EN, DEV_26_BASE => base_io_trng_c,
|
||||
DEV_27_EN => IO_WDT_EN, DEV_27_BASE => base_io_wdt_c,
|
||||
DEV_28_EN => io_gpio_en_c, DEV_28_BASE => base_io_gpio_c,
|
||||
DEV_29_EN => IO_NEOLED_EN, DEV_29_BASE => base_io_neoled_c,
|
||||
DEV_30_EN => io_sysinfo_en_c, DEV_30_BASE => base_io_sysinfo_c,
|
||||
DEV_31_EN => OCD_EN, DEV_31_BASE => base_io_ocd_c
|
||||
)
|
||||
port map (
|
||||
clk_i => clk_i,
|
||||
rstn_i => rstn_sys,
|
||||
main_req_i => io_req,
|
||||
main_rsp_o => io_rsp,
|
||||
dev_00_req_o => iodev_req(IODEV_BOOTROM), dev_00_rsp_i => iodev_rsp(IODEV_BOOTROM),
|
||||
dev_01_req_o => open, dev_01_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_02_req_o => open, dev_02_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_03_req_o => open, dev_03_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_04_req_o => open, dev_04_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_05_req_o => open, dev_05_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_06_req_o => open, dev_06_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_07_req_o => open, dev_07_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_08_req_o => open, dev_08_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_09_req_o => open, dev_09_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_10_req_o => iodev_req(IODEV_TWD), dev_10_rsp_i => iodev_rsp(IODEV_TWD),
|
||||
dev_11_req_o => iodev_req(IODEV_CFS), dev_11_rsp_i => iodev_rsp(IODEV_CFS),
|
||||
dev_12_req_o => iodev_req(IODEV_SLINK), dev_12_rsp_i => iodev_rsp(IODEV_SLINK),
|
||||
dev_13_req_o => iodev_req(IODEV_DMA), dev_13_rsp_i => iodev_rsp(IODEV_DMA),
|
||||
dev_14_req_o => iodev_req(IODEV_CRC), dev_14_rsp_i => iodev_rsp(IODEV_CRC),
|
||||
dev_15_req_o => open, dev_15_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_16_req_o => iodev_req(IODEV_PWM), dev_16_rsp_i => iodev_rsp(IODEV_PWM),
|
||||
dev_17_req_o => iodev_req(IODEV_GPTMR), dev_17_rsp_i => iodev_rsp(IODEV_GPTMR),
|
||||
dev_18_req_o => iodev_req(IODEV_ONEWIRE), dev_18_rsp_i => iodev_rsp(IODEV_ONEWIRE),
|
||||
dev_19_req_o => open, dev_19_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_20_req_o => iodev_req(IODEV_CLINT), dev_20_rsp_i => iodev_rsp(IODEV_CLINT),
|
||||
dev_21_req_o => iodev_req(IODEV_UART0), dev_21_rsp_i => iodev_rsp(IODEV_UART0),
|
||||
dev_22_req_o => iodev_req(IODEV_UART1), dev_22_rsp_i => iodev_rsp(IODEV_UART1),
|
||||
dev_23_req_o => iodev_req(IODEV_SDI), dev_23_rsp_i => iodev_rsp(IODEV_SDI),
|
||||
dev_24_req_o => iodev_req(IODEV_SPI), dev_24_rsp_i => iodev_rsp(IODEV_SPI),
|
||||
dev_25_req_o => iodev_req(IODEV_TWI), dev_25_rsp_i => iodev_rsp(IODEV_TWI),
|
||||
dev_26_req_o => iodev_req(IODEV_TRNG), dev_26_rsp_i => iodev_rsp(IODEV_TRNG),
|
||||
dev_27_req_o => iodev_req(IODEV_WDT), dev_27_rsp_i => iodev_rsp(IODEV_WDT),
|
||||
dev_28_req_o => iodev_req(IODEV_GPIO), dev_28_rsp_i => iodev_rsp(IODEV_GPIO),
|
||||
dev_29_req_o => iodev_req(IODEV_NEOLED), dev_29_rsp_i => iodev_rsp(IODEV_NEOLED),
|
||||
dev_30_req_o => iodev_req(IODEV_SYSINFO), dev_30_rsp_i => iodev_rsp(IODEV_SYSINFO),
|
||||
dev_31_req_o => iodev_req(IODEV_OCD), dev_31_rsp_i => iodev_rsp(IODEV_OCD)
|
||||
dev_00_req_o => iodev_req(IODEV_BOOTROM), dev_00_rsp_i => iodev_rsp(IODEV_BOOTROM),
|
||||
dev_01_req_o => open, dev_01_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_02_req_o => open, dev_02_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_03_req_o => open, dev_03_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_04_req_o => open, dev_04_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_05_req_o => open, dev_05_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_06_req_o => open, dev_06_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_07_req_o => open, dev_07_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_08_req_o => open, dev_08_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_09_req_o => open, dev_09_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_10_req_o => iodev_req(IODEV_TWD), dev_10_rsp_i => iodev_rsp(IODEV_TWD),
|
||||
dev_11_req_o => iodev_req(IODEV_CFS), dev_11_rsp_i => iodev_rsp(IODEV_CFS),
|
||||
dev_12_req_o => iodev_req(IODEV_SLINK), dev_12_rsp_i => iodev_rsp(IODEV_SLINK),
|
||||
dev_13_req_o => iodev_req(IODEV_DMA), dev_13_rsp_i => iodev_rsp(IODEV_DMA),
|
||||
dev_14_req_o => iodev_req(IODEV_CRC), dev_14_rsp_i => iodev_rsp(IODEV_CRC),
|
||||
dev_15_req_o => open, dev_15_rsp_i => rsp_terminate_c, -- reserved
|
||||
dev_16_req_o => iodev_req(IODEV_PWM), dev_16_rsp_i => iodev_rsp(IODEV_PWM),
|
||||
dev_17_req_o => iodev_req(IODEV_GPTMR), dev_17_rsp_i => iodev_rsp(IODEV_GPTMR),
|
||||
dev_18_req_o => iodev_req(IODEV_ONEWIRE), dev_18_rsp_i => iodev_rsp(IODEV_ONEWIRE),
|
||||
dev_19_req_o => iodev_req(IODEV_HWSPINLOCK), dev_19_rsp_i => iodev_rsp(IODEV_HWSPINLOCK),
|
||||
dev_20_req_o => iodev_req(IODEV_CLINT), dev_20_rsp_i => iodev_rsp(IODEV_CLINT),
|
||||
dev_21_req_o => iodev_req(IODEV_UART0), dev_21_rsp_i => iodev_rsp(IODEV_UART0),
|
||||
dev_22_req_o => iodev_req(IODEV_UART1), dev_22_rsp_i => iodev_rsp(IODEV_UART1),
|
||||
dev_23_req_o => iodev_req(IODEV_SDI), dev_23_rsp_i => iodev_rsp(IODEV_SDI),
|
||||
dev_24_req_o => iodev_req(IODEV_SPI), dev_24_rsp_i => iodev_rsp(IODEV_SPI),
|
||||
dev_25_req_o => iodev_req(IODEV_TWI), dev_25_rsp_i => iodev_rsp(IODEV_TWI),
|
||||
dev_26_req_o => iodev_req(IODEV_TRNG), dev_26_rsp_i => iodev_rsp(IODEV_TRNG),
|
||||
dev_27_req_o => iodev_req(IODEV_WDT), dev_27_rsp_i => iodev_rsp(IODEV_WDT),
|
||||
dev_28_req_o => iodev_req(IODEV_GPIO), dev_28_rsp_i => iodev_rsp(IODEV_GPIO),
|
||||
dev_29_req_o => iodev_req(IODEV_NEOLED), dev_29_rsp_i => iodev_rsp(IODEV_NEOLED),
|
||||
dev_30_req_o => iodev_req(IODEV_SYSINFO), dev_30_rsp_i => iodev_rsp(IODEV_SYSINFO),
|
||||
dev_31_req_o => iodev_req(IODEV_OCD), dev_31_rsp_i => iodev_rsp(IODEV_OCD)
|
||||
);
|
||||
|
||||
|
||||
|
|
@ -1570,6 +1572,25 @@ begin
|
|||
end generate;
|
||||
|
||||
|
||||
-- Hardware Spinlocks (HWSPINLOCK) --------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_hwspinlock_enabled:
|
||||
if IO_HWSPINLOCK_EN generate
|
||||
neorv32_hwspinlock_inst: entity neorv32.neorv32_hwspinlock
|
||||
port map (
|
||||
clk_i => clk_i,
|
||||
rstn_i => rstn_sys,
|
||||
bus_req_i => iodev_req(IODEV_HWSPINLOCK),
|
||||
bus_rsp_o => iodev_rsp(IODEV_HWSPINLOCK)
|
||||
);
|
||||
end generate;
|
||||
|
||||
neorv32_hwspinlock_disabled:
|
||||
if not IO_HWSPINLOCK_EN generate
|
||||
iodev_rsp(IODEV_HWSPINLOCK) <= rsp_terminate_c;
|
||||
end generate;
|
||||
|
||||
|
||||
-- System Configuration Information Memory (SYSINFO) --------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_sysinfo_enabled:
|
||||
|
|
@ -1614,7 +1635,8 @@ begin
|
|||
IO_ONEWIRE_EN => IO_ONEWIRE_EN,
|
||||
IO_DMA_EN => IO_DMA_EN,
|
||||
IO_SLINK_EN => IO_SLINK_EN,
|
||||
IO_CRC_EN => IO_CRC_EN
|
||||
IO_CRC_EN => IO_CRC_EN,
|
||||
IO_HWSPINLOCK_EN => IO_HWSPINLOCK_EN
|
||||
)
|
||||
port map (
|
||||
clk_i => clk_i,
|
||||
|
|
|
|||
|
|
@ -222,7 +222,8 @@ begin
|
|||
IO_SLINK_EN => true,
|
||||
IO_SLINK_RX_FIFO => 4,
|
||||
IO_SLINK_TX_FIFO => 4,
|
||||
IO_CRC_EN => true
|
||||
IO_CRC_EN => true,
|
||||
IO_HWSPINLOCK_EN => true
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue