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[sw/example/demo_gptmr] code clean-up, typo fixes

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stnolting 2022-01-30 05:55:53 +01:00
parent a4a66a36f0
commit cf35e4034c
1 changed files with 10 additions and 10 deletions
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20
sw/example/demo_gptmr/main.c
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@ -3,7 +3,7 @@
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
@ -67,7 +67,7 @@ int main() {
// capture all exceptions and give debug info via UART
neorv32_rte_setup();
// init UART at default baud rate, no parity bits, ho hw flow control
// init UART at default baud rate, no parity bits, no HW flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
@ -89,18 +89,18 @@ int main() {
// install GPTMR interrupt handler
neorv32_rte_exception_install(GPTMR_RTE_ID, gptmr_firq_handler);
// configure timer for 1Hz in continuous mode
uint32_t soc_clock = NEORV32_SYSINFO.CLK;
soc_clock = soc_clock / 2; // divide by two as we are using the 1/2 clock prescaler
neorv32_gptmr_setup(CLK_PRSC_2, 1, soc_clock);
// configure timer for 1Hz ticks in continuous mode (with clock divisor = 8)
neorv32_gptmr_setup(CLK_PRSC_8, 1, NEORV32_SYSINFO.CLK / 8);
// enable interrupt
neorv32_cpu_irq_enable(GPTMR_FIRQ_ENABLE); // enable GPTRM FIRQ channel
neorv32_cpu_irq_enable(GPTMR_FIRQ_ENABLE); // enable GPTMR FIRQ channel
neorv32_cpu_eint(); // enable global interrupt flag
// do nothing, wait for interrupt
while(1);
// go to sleep mode and wait for interrupt
while(1) {
neorv32_cpu_sleep();
}
return 0;
}
@ -115,6 +115,6 @@ void gptmr_firq_handler(void) {
neorv32_cpu_csr_write(CSR_MIP, 1<<GPTMR_FIRQ_PENDING); // clear/ack pending FIRQ
neorv32_uart0_putc('.'); // send tick symbol via UART
neorv32_uart0_putc('.'); // send tick symbol via UART0
neorv32_gpio_pin_toggle(0); // toggle output port bit 0
}