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removed option (CSR_COUNTER_USE) to disable CSR counter since they are mandatory according to RISC-V spec

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stnolting 2020-09-11 22:54:12 +02:00
parent 1d2058e91d
commit cfa3413d03
7 changed files with 40 additions and 72 deletions
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2
README.md
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@ -382,7 +382,6 @@ entity neorv32_cpu is
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
@ -447,7 +446,6 @@ entity neorv32_top is
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?

4
rtl/core/neorv32_cpu.vhd
View file

@ -63,7 +63,6 @@ entity neorv32_cpu is
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
@ -155,8 +154,6 @@ begin
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
-- PMP requires Zicsr extension --
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
-- performance counters require Zicsr extension --
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CSR_COUNTERS_USE = true)) report "NEORV32 CPU CONFIG ERROR! Performance counter CSRs require CPU_EXTENSION_RISCV_Zicsr extension." severity error;
-- PMP regions --
assert not ((PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range." severity error;
-- PMP granulartiy --
@ -170,7 +167,6 @@ begin
neorv32_cpu_control_inst: neorv32_cpu_control
generic map (
-- General --
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
-- RISC-V CPU Extensions --

95
rtl/core/neorv32_cpu_control.vhd
View file

@ -46,7 +46,6 @@ use neorv32.neorv32_package.all;
entity neorv32_cpu_control is
generic (
-- General --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
-- RISC-V CPU Extensions --
@ -239,7 +238,6 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
signal mcycle_msb : std_ulogic;
signal minstret_msb : std_ulogic;
signal systime : std_ulogic_vector(63 downto 0);
-- illegal instruction check --
signal illegal_instruction : std_ulogic;
@ -965,17 +963,17 @@ begin
when x"3b6" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 7)) and is_m_mode_v; -- pmpaddr6
when x"3b7" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 8)) and is_m_mode_v; -- pmpaddr7
--
when x"c00" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- cycle
when x"c01" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- time
when x"c02" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- instret
when x"c80" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- cycleh
when x"c81" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- timeh
when x"c82" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- instreth
when x"c00" => csr_acc_valid <= '1'; -- cycle
when x"c01" => csr_acc_valid <= '1'; -- time
when x"c02" => csr_acc_valid <= '1'; -- instret
when x"c80" => csr_acc_valid <= '1'; -- cycleh
when x"c81" => csr_acc_valid <= '1'; -- timeh
when x"c82" => csr_acc_valid <= '1'; -- instreth
--
when x"b00" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE) and is_m_mode_v; -- mcycle
when x"b02" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE) and is_m_mode_v; -- minstret
when x"b80" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE) and is_m_mode_v; -- mcycleh
when x"b82" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE) and is_m_mode_v; -- minstreth
when x"b00" => csr_acc_valid <= is_m_mode_v; -- mcycle
when x"b02" => csr_acc_valid <= is_m_mode_v; -- minstret
when x"b80" => csr_acc_valid <= is_m_mode_v; -- mcycleh
when x"b82" => csr_acc_valid <= is_m_mode_v; -- minstreth
--
when x"f11" => csr_acc_valid <= is_m_mode_v; -- mvendorid
when x"f12" => csr_acc_valid <= is_m_mode_v; -- marchid
@ -1671,13 +1669,13 @@ begin
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
csr_rdata_o <= csr.mcycle(31 downto 0);
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
csr_rdata_o <= systime(31 downto 0);
csr_rdata_o <= time_i(31 downto 0);
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW
csr_rdata_o <= csr.minstret(31 downto 0);
when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH
csr_rdata_o <= x"000" & csr.mcycleh(19 downto 0); -- only the lowest 20 bit!
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
csr_rdata_o <= systime(63 downto 32);
csr_rdata_o <= time_i(63 downto 32);
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit!
@ -1695,7 +1693,6 @@ begin
when x"fc0" => -- R/-: mzext
csr_rdata_o(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr CPU extension
csr_rdata_o(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei CPU extension
csr_rdata_o(2) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- std (performance) counters enabled
-- undefined/unavailable --
when others =>
@ -1708,9 +1705,6 @@ begin
end if;
end process csr_read_access;
-- time[h] CSR --
systime <= time_i when (CSR_COUNTERS_USE = true) else (others => '0');
-- CPU's current privilege level --
priv_mode_o <= csr.privilege;
@ -1740,47 +1734,36 @@ begin
mcycle_msb <= '0';
minstret_msb <= '0';
elsif rising_edge(clk_i) then
if (CSR_COUNTERS_USE = true) then
-- mcycle (cycle) --
mcycle_msb <= csr.mcycle(csr.mcycle'left);
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access
csr.mcycle(31 downto 0) <= csr_wdata_i;
csr.mcycle(32) <= '0';
elsif (execute_engine.sleep = '0') then -- automatic update
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
end if;
-- mcycle (cycle) --
mcycle_msb <= csr.mcycle(csr.mcycle'left);
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access
csr.mcycle(31 downto 0) <= csr_wdata_i;
csr.mcycle(32) <= '0';
elsif (execute_engine.sleep = '0') then -- automatic update
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
end if;
-- mcycleh (cycleh) --
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
csr.mcycleh <= csr_wdata_i(csr.mcycleh'left downto 0);
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
end if;
-- mcycleh (cycleh) --
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
csr.mcycleh <= csr_wdata_i(19 downto 0);
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
end if;
-- minstret (instret) --
minstret_msb <= csr.minstret(csr.minstret'left);
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
csr.minstret(31 downto 0) <= csr_wdata_i;
csr.minstret(32) <= '0';
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
end if;
-- minstret (instret) --
minstret_msb <= csr.minstret(csr.minstret'left);
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
csr.minstret(31 downto 0) <= csr_wdata_i;
csr.minstret(32) <= '0';
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
end if;
-- minstreth (instreth) --
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
csr.minstreth <= csr_wdata_i(19 downto 0);
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
end if;
else -- if not implemented
csr.mcycle <= (others => '0');
csr.minstret <= (others => '0');
csr.mcycleh <= (others => '0');
csr.minstreth <= (others => '0');
mcycle_msb <= '0';
minstret_msb <= '0';
-- minstreth (instreth) --
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
csr.minstreth <= csr_wdata_i(csr.minstreth'left downto 0);
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
end if;
end if;
end process csr_counters;

5
rtl/core/neorv32_package.vhd
View file

@ -41,7 +41,7 @@ package neorv32_package is
-- Architecture Constants/Configuration ---------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - FIXED!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040004"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040005"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
@ -395,7 +395,6 @@ package neorv32_package is
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
@ -481,7 +480,6 @@ package neorv32_package is
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
@ -532,7 +530,6 @@ package neorv32_package is
component neorv32_cpu_control
generic (
-- General --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
-- RISC-V CPU Extensions --

2
rtl/core/neorv32_top.vhd
View file

@ -59,7 +59,6 @@ entity neorv32_top is
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Extension Options --
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
@ -308,7 +307,6 @@ begin
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Extension Options --
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
-- Physical Memory Protection (PMP) --
PMP_USE => PMP_USE, -- implement PMP?

1
sim/neorv32_tb.vhd
View file

@ -140,7 +140,6 @@ begin
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
-- Extension Options --
CSR_COUNTERS_USE => true, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
-- Physical Memory Protection (PMP) --
PMP_USE => true, -- implement PMP?

3
sw/lib/source/neorv32_rte.c
View file

@ -298,9 +298,6 @@ void neorv32_rte_print_hw_config(void) {
if (tmp & (1<<1)) {
neorv32_uart_printf("Zifencei ");
}
if (tmp & (1<<2)) {
neorv32_uart_printf("cpu_counters ");
}
// Misc