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[test_setups] update GPIO port sizes
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stnolting 2025-01-19 20:50:13 +01:00
parent 87a78de173
commit d043b71b56
3 changed files with 9 additions and 9 deletions
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6
rtl/test_setups/neorv32_test_setup_approm.vhd
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@ -3,7 +3,7 @@
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
@ -33,7 +33,7 @@ end entity;
architecture neorv32_test_setup_approm_rtl of neorv32_test_setup_approm is
signal con_gpio_out : std_ulogic_vector(63 downto 0);
signal con_gpio_out : std_ulogic_vector(31 downto 0);
begin
@ -56,7 +56,7 @@ begin
MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64)
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..32)
IO_CLINT_EN => true -- implement core local interruptor (CLINT)?
)
port map (

6
rtl/test_setups/neorv32_test_setup_bootloader.vhd
View file

@ -3,7 +3,7 @@
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
@ -36,7 +36,7 @@ end entity;
architecture neorv32_test_setup_bootloader_rtl of neorv32_test_setup_bootloader is
signal con_gpio_out : std_ulogic_vector(63 downto 0);
signal con_gpio_out : std_ulogic_vector(31 downto 0);
begin
@ -59,7 +59,7 @@ begin
MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64)
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..32)
IO_CLINT_EN => true, -- implement core local interruptor (CLINT)?
IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)?
)

6
rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd
View file

@ -3,7 +3,7 @@
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
@ -41,7 +41,7 @@ end entity;
architecture neorv32_test_setup_on_chip_debugger_rtl of neorv32_test_setup_on_chip_debugger is
signal con_gpio_out : std_ulogic_vector(63 downto 0);
signal con_gpio_out : std_ulogic_vector(31 downto 0);
begin
@ -67,7 +67,7 @@ begin
MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64)
IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..32)
IO_CLINT_EN => true, -- implement core local interruptor (CLINT)?
IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)?
)