[docs] minor link fixes

docs/datasheet/overview.adoc

@@ -103,19 +103,19 @@ Links in this document are <<_structure,highlighted>>.
 ...................................
 neorv32            - Project home folder
 ├.ci              - Scripts for continuous integration
-├boards           - Example setups for various FPGA boards
-│├osflow         - Makefile based plumbing for open source EDA tooling (GHDL, yosys, nextpnr, icestorm, etc.)
+├setups           - Example setups for various FPGA boards and toolchains **WORK IN PROGRESS**
 ├CHANGELOG.md     - Project change log
 ├docs             - Project documentation
 │├doxygen_build  - Software framework documentation (generated by doxygen)
 │├src_adoc       - AsciiDoc sources for this document
 │├references     - Data sheets and RISC-V specs.
 │└figures        - Figures and logos
-├examples         - Ready-to-use top entities for the supported boards and entrypoint for generating bitstreams
 ├riscv-arch-test  - Port files for the official RISC-V architecture tests
 ├rtl              - VHDL sources
 │├core           - Sources of the CPU & SoC
 │└templates      - Alternate/additional top entities/wrappers
+│ ├processor      - Processor wrappers
+│ └system         - System wrappers for advanced connectivity
 ├sim              - Simulation files
 │├ghdl           - Simulation scripts for GHDL
 │├rtl_modules    - Processor modules for simulation-only
@@ -266,8 +266,8 @@ between entity boundaries, so the actual utilization results might vary a bit.
 ==== Exemplary Setups
 
 [TIP]
-Exemplary setups for different technologies and various FPGA boards can be found in the `boards` folder
-(https://github.com/stnolting/neorv32/tree/master/boards).
+Check out the example setups in the `setup` folder  (@GitHub: https://github.com/stnolting/neorv32/tree/master/setups),
+which provides script-based demo projects for various FPGA boards and toolchains.
 
 The following table shows exemplary NEORV32 processor implementation results for different FPGA
 platforms. Most setups use the default peripheral configuration (like no CFS, no caches and no

docs/userguide/content.adoc

@@ -125,8 +125,8 @@ The following steps are required to generate a bitstream for your FPGA board. If
 NEORV32 processor in simulation only, the following steps might also apply.
 
 [TIP]
-Check out the example setups in the `boards` folder  (@GitHub: https://github.com/stnolting/neorv32/tree/master/boards), which provides script-based
-demo projects for various FPGA boars.
+Check out the example setups in the `setup` folder  (@GitHub: https://github.com/stnolting/neorv32/tree/master/setups),
+which provides script-based demo projects for various FPGA boards and toolchains.
 
 In this tutorial we will use a test implementation of the processor – using many of the processor's optional
 modules but just propagating the minimal signals to the outer world. Hence, this guide is intended as