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[rtl] WISHBONE: assertion cleanup

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stnolting 2023-11-09 17:31:12 +01:00
parent be9579c5eb
commit d26c3b700b
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rtl/core/neorv32_wishbone.vhd
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@ -118,7 +118,7 @@ begin
assert false report
"NEORV32 PROCESSOR CONFIG NOTE: Ext. Bus Interface - " &
cond_sel_string_f(PIPE_MODE, "PIPELINED", "CLASSIC/STANDARD") & " Wishbone protocol, " &
cond_sel_string_f(boolean(BUS_TIMEOUT /= 0), "auto-timeout (" & integer'image(BUS_TIMEOUT) & " cycles), ", "NO auto-timeout, ") &
cond_sel_string_f(boolean(BUS_TIMEOUT /= 0), "auto-timeout, ", "NO auto-timeout, ") &
cond_sel_string_f(BIG_ENDIAN, "BIG", "LITTLE") & "-endian byte order, " &
cond_sel_string_f(async_rx_c, "ASYNC ", "registered ") & "RX, " &
cond_sel_string_f(ASYNC_TX, "ASYNC ", "registered ") & "TX"