mirror of
https://github.com/stnolting/neorv32.git
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[sw] update onewire HAL
This commit is contained in:
stnolting
parent
38fd3b7f9b
commit
d307bf5fa1
3 changed files with 101 additions and 77 deletions
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@ -12,22 +12,23 @@
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#define TRUE 1
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static unsigned char dscrc_table[] = {
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0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,
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157,195, 33,127,252,162, 64, 30, 95, 1,227,189, 62, 96,130,220,
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35,125,159,193, 66, 28,254,160,225,191, 93, 3,128,222, 60, 98,
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190,224, 2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,
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70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89, 7,
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219,133,103, 57,186,228, 6, 88, 25, 71,165,251,120, 38,196,154,
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101, 59,217,135, 4, 90,184,230,167,249, 27, 69,198,152,122, 36,
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248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91, 5,231,185,
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140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,
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17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,
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175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,
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50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,
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202,148,118, 40,171,245, 23, 73, 8, 86,180,234,105, 55,213,139,
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87, 9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,
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233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,
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116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53};
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0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,
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157,195, 33,127,252,162, 64, 30, 95, 1,227,189, 62, 96,130,220,
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35,125,159,193, 66, 28,254,160,225,191, 93, 3,128,222, 60, 98,
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190,224, 2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,
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70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89, 7,
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219,133,103, 57,186,228, 6, 88, 25, 71,165,251,120, 38,196,154,
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101, 59,217,135, 4, 90,184,230,167,249, 27, 69,198,152,122, 36,
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248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91, 5,231,185,
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140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,
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17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,
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175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,
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50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,
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202,148,118, 40,171,245, 23, 73, 8, 86,180,234,105, 55,213,139,
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87, 9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,
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233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,
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116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53
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};
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// method declarations
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int OWFirst();
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@ -105,8 +106,8 @@ int OWSearch()
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return FALSE;
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}
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// issue the search command
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neorv32_onewire_write_byte_blocking(0xF0);
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// issue the search command
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neorv32_onewire_write_byte_blocking(0xF0);
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// loop to do the search
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do
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@ -179,7 +180,7 @@ int OWSearch()
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// check for last device
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if (LastDiscrepancy == 0)
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LastDeviceFlag = TRUE;
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search_result = TRUE;
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}
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}
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@ -233,7 +234,7 @@ int OWVerify()
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else
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rslt = FALSE;
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// restore the search state
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// restore the search state
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for (i = 0; i < 8; i++)
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ROM_NO[i] = rom_backup[i];
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LastDiscrepancy = ld_backup;
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@ -277,17 +278,17 @@ void OWFamilySkipSetup()
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}
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//--------------------------------------------------------------------------
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// Calculate the CRC8 of the byte value provided with the current
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// global 'crc8' value.
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// Calculate the CRC8 of the byte value provided with the current
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// global 'crc8' value.
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// Returns current global crc8 value
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//
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unsigned char docrc8(unsigned char value)
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{
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// See Application Note 27
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// TEST BUILD
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crc8 = dscrc_table[crc8 ^ value];
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return crc8;
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}
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#endif // onewire_aux_h
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#endif // onewire_aux_h
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@ -28,7 +28,7 @@
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/** ONEWIRE module prototype */
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typedef volatile struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_ONEWIRE_CTRL_enum) */
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uint32_t DATA; /**< offset 4: transmission data register (#NEORV32_ONEWIRE_DATA_enum) */
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uint32_t DCMD; /**< offset 4: command and data register (#NEORV32_ONEWIRE_DCMD_enum) */
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} neorv32_onewire_t;
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/** ONEWIRE module hardware access (#neorv32_onewire_t) */
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@ -37,41 +37,53 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
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/** ONEWIRE control register bits */
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enum NEORV32_ONEWIRE_CTRL_enum {
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ONEWIRE_CTRL_EN = 0, /**< ONEWIRE control register(0) (r/w): ONEWIRE controller enable */
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ONEWIRE_CTRL_PRSC0 = 1, /**< ONEWIRE control register(1) (r/w): Clock prescaler select bit 0 */
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ONEWIRE_CTRL_PRSC1 = 2, /**< ONEWIRE control register(2) (r/w): Clock prescaler select bit 1 */
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ONEWIRE_CTRL_CLKDIV0 = 3, /**< ONEWIRE control register(3) (r/w): Clock divider bit 0 */
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ONEWIRE_CTRL_CLKDIV1 = 4, /**< ONEWIRE control register(4) (r/w): Clock divider bit 1 */
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ONEWIRE_CTRL_CLKDIV2 = 5, /**< ONEWIRE control register(5) (r/w): Clock divider bit 2 */
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ONEWIRE_CTRL_CLKDIV3 = 6, /**< ONEWIRE control register(6) (r/w): Clock divider bit 3 */
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ONEWIRE_CTRL_CLKDIV4 = 7, /**< ONEWIRE control register(7) (r/w): Clock divider bit 4 */
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ONEWIRE_CTRL_CLKDIV5 = 8, /**< ONEWIRE control register(8) (r/w): Clock divider bit 5 */
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ONEWIRE_CTRL_CLKDIV6 = 9, /**< ONEWIRE control register(9) (r/w): Clock divider bit 6 */
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ONEWIRE_CTRL_CLKDIV7 = 10, /**< ONEWIRE control register(10) (r/w): Clock divider bit 7 */
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ONEWIRE_CTRL_TRIG_RST = 11, /**< ONEWIRE control register(11) (-/w): Trigger reset pulse, auto-clears */
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ONEWIRE_CTRL_TRIG_BIT = 12, /**< ONEWIRE control register(12) (-/w): Trigger single-bit transmission, auto-clears */
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ONEWIRE_CTRL_TRIG_BYTE = 13, /**< ONEWIRE control register(13) (-/w): Trigger full-byte transmission, auto-clears */
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ONEWIRE_CTRL_CLEAR = 1, /**< ONEWIRE control register(1) (-/w): Clear RXT FIFO, auto-clears */
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ONEWIRE_CTRL_PRSC0 = 2, /**< ONEWIRE control register(2) (r/w): Clock prescaler select bit 0 */
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ONEWIRE_CTRL_PRSC1 = 3, /**< ONEWIRE control register(3) (r/w): Clock prescaler select bit 1 */
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ONEWIRE_CTRL_CLKDIV0 = 4, /**< ONEWIRE control register(4) (r/w): Clock divider bit 0 */
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ONEWIRE_CTRL_CLKDIV7 = 11, /**< ONEWIRE control register(11) (r/w): Clock divider bit 7 */
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ONEWIRE_CTRL_SENSE = 29, /**< ONEWIRE control register(29) (r/-): Current state of the bus line */
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ONEWIRE_CTRL_PRESENCE = 30, /**< ONEWIRE control register(30) (r/-): Bus presence detected */
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ONEWIRE_CTRL_FIFO_LSB = 15, /**< ONEWIRE control register(15) (r/-): log2(FIFO size), LSB */
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ONEWIRE_CTRL_FIFO_MSB = 18, /**< ONEWIRE control register(18) (r/-): log2(FIFO size), MSB */
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ONEWIRE_CTRL_TX_FULL = 28, /**< ONEWIRE control register(28) (r/-): TX FIFO full */
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ONEWIRE_CTRL_RX_AVAIL = 29, /**< ONEWIRE control register(29) (r/-): RX FIFO data available */
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ONEWIRE_CTRL_SENSE = 30, /**< ONEWIRE control register(30) (r/-): Current state of the bus line */
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ONEWIRE_CTRL_BUSY = 31, /**< ONEWIRE control register(31) (r/-): Operation in progress when set */
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};
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/** ONEWIRE receive/transmit data register bits */
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enum NEORV32_ONEWIRE_DATA_enum {
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ONEWIRE_DATA_LSB = 0, /**< ONEWIRE data register(0) (r/w): Receive/transmit data (8-bit) LSB */
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ONEWIRE_DATA_MSB = 7 /**< ONEWIRE data register(7) (r/w): Receive/transmit data (8-bit) MSB */
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/** ONEWIRE command and data register bits */
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enum NEORV32_ONEWIRE_DCMD_enum {
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ONEWIRE_DCMD_DATA_LSB = 0, /**< ONEWIRE data/data register(0) (r/w): Receive/transmit data (8-bit) LSB */
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ONEWIRE_DCMD_DATA_MSB = 7, /**< ONEWIRE data/data register(7) (r/w): Receive/transmit data (8-bit) MSB */
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ONEWIRE_DCMD_CMD_LO = 8, /**< ONEWIRE data/data register(8) (-/w): Operation command LSB */
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ONEWIRE_DCMD_CMD_HI = 9, /**< ONEWIRE data/data register(9) (-/w): Operation command MSB */
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ONEWIRE_DCMD_PRESENCE = 10 /**< ONEWIRE data/data register(10) (r/-): Bus presence detected */
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};
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/**@}*/
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/**********************************************************************//**
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* @name ONEWIRE DCMD commands
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**************************************************************************/
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/**@{*/
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#define ONEWIRE_CMD_NOP (0b00) // no operation
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#define ONEWIRE_CMD_BIT (0b01) // read/write single bit
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#define ONEWIRE_CMD_BYTE (0b10) // read/write full byte
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#define ONEWIRE_CMD_RESET (0b11) // generate reset pulse and check for presence
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/**@}*/
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/**********************************************************************//**
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* @name Prototypes
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**************************************************************************/
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/**@{*/
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int neorv32_onewire_available(void);
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int neorv32_onewire_get_fifo_depth(void);
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int neorv32_onewire_setup(uint32_t t_base);
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void neorv32_onewire_enable(void);
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void neorv32_onewire_disable(void);
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void neorv32_onewire_flush(void);
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int neorv32_onewire_sense(void);
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int neorv32_onewire_busy(void);
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@ -34,6 +34,18 @@ int neorv32_onewire_available(void) {
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}
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/**********************************************************************//**
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* Get ONEWIRE FIFO depth.
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*
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* @return FIFO depth (number of entries), zero if no FIFO implemented
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**************************************************************************/
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int neorv32_onewire_get_fifo_depth(void) {
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uint32_t tmp = (NEORV32_ONEWIRE->CTRL >> ONEWIRE_CTRL_FIFO_LSB) & 0x0f;
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return (int)(1 << tmp);
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}
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/**********************************************************************//**
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* Reset, configure and enable ONEWIRE interface controller.
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*
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@ -46,7 +58,6 @@ int neorv32_onewire_setup(uint32_t t_base) {
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// reset
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NEORV32_ONEWIRE->CTRL = 0;
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NEORV32_ONEWIRE->DATA = 0;
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uint32_t t_tick;
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uint32_t clkdiv;
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@ -99,6 +110,15 @@ void neorv32_onewire_disable(void) {
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}
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/**********************************************************************//**
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* Clear RTX FIFO.
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**************************************************************************/
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void neorv32_onewire_flush(void) {
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NEORV32_ONEWIRE->CTRL &= ~(1 << ONEWIRE_CTRL_CLEAR);
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}
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/**********************************************************************//**
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* Get current bus state.
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*
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@ -114,17 +134,9 @@ int neorv32_onewire_sense(void) {
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}
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}
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// ----------------------------------------------------------------------------------------------------------------------------
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// NON-BLOCKING functions
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// ----------------------------------------------------------------------------------------------------------------------------
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/**********************************************************************//**
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* Check if ONEWIRE module is busy.
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*
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* @note This function is non-blocking.
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*
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* @return 0 if not busy, 1 if busy.
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**************************************************************************/
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int neorv32_onewire_busy(void) {
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@ -139,6 +151,11 @@ int neorv32_onewire_busy(void) {
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}
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// ----------------------------------------------------------------------------------------------------------------------------
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// NON-BLOCKING functions
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// ----------------------------------------------------------------------------------------------------------------------------
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/**********************************************************************//**
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* Initiate reset pulse.
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*
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@ -147,7 +164,7 @@ int neorv32_onewire_busy(void) {
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void neorv32_onewire_reset(void) {
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// trigger reset-pulse operation
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NEORV32_ONEWIRE->CTRL |= 1 << ONEWIRE_CTRL_TRIG_RST;
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NEORV32_ONEWIRE->DCMD = ONEWIRE_CMD_RESET << ONEWIRE_DCMD_CMD_LO;
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}
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@ -161,7 +178,7 @@ void neorv32_onewire_reset(void) {
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int neorv32_onewire_reset_get_presence(void) {
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// check presence bit
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if (NEORV32_ONEWIRE->CTRL & (1 << ONEWIRE_CTRL_PRESENCE)) {
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if (NEORV32_ONEWIRE->DCMD & (1 << ONEWIRE_DCMD_PRESENCE)) {
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return 0;
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}
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else {
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@ -177,11 +194,8 @@ int neorv32_onewire_reset_get_presence(void) {
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**************************************************************************/
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void neorv32_onewire_read_bit(void) {
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// output all-one
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NEORV32_ONEWIRE->DATA = 0xff;
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// trigger bit operation
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NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_TRIG_BIT);
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// trigger bit operation with data = all-one
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NEORV32_ONEWIRE->DCMD = (ONEWIRE_CMD_BIT << ONEWIRE_DCMD_CMD_LO) | (0xff << ONEWIRE_DCMD_DATA_LSB);
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}
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@ -195,7 +209,7 @@ void neorv32_onewire_read_bit(void) {
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uint8_t neorv32_onewire_read_bit_get(void) {
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// return read bit
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if (NEORV32_ONEWIRE->DATA & (1 << 7)) { // LSB first -> read bit is in MSB
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if (NEORV32_ONEWIRE->DCMD & (1 << ONEWIRE_DCMD_DATA_MSB)) { // LSB first -> read bit is in MSB
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return 1;
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}
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else {
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@ -213,16 +227,13 @@ uint8_t neorv32_onewire_read_bit_get(void) {
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**************************************************************************/
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void neorv32_onewire_write_bit(uint8_t bit) {
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// set replicated bit
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// set replicated bit and trigger bit operation
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if (bit) {
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NEORV32_ONEWIRE->DATA = 0xff;
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NEORV32_ONEWIRE->DCMD = (ONEWIRE_CMD_BIT << ONEWIRE_DCMD_CMD_LO) | (0xff << ONEWIRE_DCMD_DATA_LSB);
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}
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else {
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NEORV32_ONEWIRE->DATA = 0x00;
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NEORV32_ONEWIRE->DCMD = (ONEWIRE_CMD_BIT << ONEWIRE_DCMD_CMD_LO) | (0x00 << ONEWIRE_DCMD_DATA_LSB);
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}
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// trigger bit operation
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NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_TRIG_BIT);
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}
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@ -233,11 +244,8 @@ void neorv32_onewire_write_bit(uint8_t bit) {
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**************************************************************************/
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void neorv32_onewire_read_byte(void) {
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// output all-one
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NEORV32_ONEWIRE->DATA = 0xff;
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//trigger byte operation
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NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_TRIG_BYTE);
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// output all-one and trigger byte operation
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NEORV32_ONEWIRE->DCMD = (ONEWIRE_CMD_BYTE << ONEWIRE_DCMD_CMD_LO) | (0xff << ONEWIRE_DCMD_DATA_LSB);
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}
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@ -251,7 +259,7 @@ void neorv32_onewire_read_byte(void) {
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uint8_t neorv32_onewire_read_byte_get(void) {
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// return read bit
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return (uint8_t)(NEORV32_ONEWIRE->DATA);
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return (uint8_t)(NEORV32_ONEWIRE->DCMD);
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}
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@ -264,11 +272,8 @@ uint8_t neorv32_onewire_read_byte_get(void) {
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**************************************************************************/
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void neorv32_onewire_write_byte(uint8_t byte) {
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// TX data
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NEORV32_ONEWIRE->DATA = (uint32_t)byte;
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// and trigger byte operation
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NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_TRIG_BYTE);
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NEORV32_ONEWIRE->DCMD = (ONEWIRE_CMD_BYTE << ONEWIRE_DCMD_CMD_LO) | ((uint32_t)byte << ONEWIRE_DCMD_DATA_LSB);
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}
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@ -331,6 +336,9 @@ void neorv32_onewire_write_bit_blocking(uint8_t bit) {
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// wait for operation to complete
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while (neorv32_onewire_busy());
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// discard received data
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neorv32_onewire_read_byte_get();
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}
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@ -368,4 +376,7 @@ void neorv32_onewire_write_byte_blocking(uint8_t byte) {
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// wait for operation to complete
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while (neorv32_onewire_busy());
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// discard received data
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neorv32_onewire_read_byte_get();
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}
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