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[docs/datasheet] minor updates, fixes, clean-ups

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stnolting 2021-06-13 17:45:26 +02:00
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docs/attrs.adoc
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@ -1,7 +1,7 @@
:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.5.6.0
:revnumber: v1.5.6.9
:doctype: book
:sectnums:
:stem:

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docs/datasheet/overview.adoc
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@ -22,28 +22,11 @@ in the root directory of the NEORV32 repository. Please also check out the <<_le
**Structure**
Chapter <<_neorv32_processor_soc>>
* top entity signals and configuration generics, address space layout, internal peripheral devices and interrupts, internal
memories and caches, internal bus architecture, external bus interface
Chapter <<_neorv32_central_processing_unit_cpu>>
* instruction set(s) and extensions, instruction timing, control and status registers, traps, exceptions and interrupts,
hardware execution safety, native bus interface
Chapter <<_on_chip_debugger_ocd>>
* on-chip debugging compatible to the "Minimal RISC-V Debug Specification Version 0.13.2".
Chapter <<_software_framework>>
* core libraries, bootloader, makefiles, runtime environment
Additional documentation: **https://stnolting.github.io/neorv32/ug[User Guide]**
* toolchain installation and setup, hardware setup, software setup, application compilation, simulating the processor
debugging using the on-chip debugger
* <<_neorv32_processor_soc>>
* <<_neorv32_central_processing_unit_cpu>>
* <<_on_chip_debugger_ocd>>
* <<_software_framework>>
* Additional documentation: **https://stnolting.github.io/neorv32/ug[User Guide]**
[TIP]
Links in this document are <<_structure,highlighted>>.

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docs/datasheet/soc.adoc
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@ -1018,11 +1018,11 @@ This read-only memory is pre-initialized with the default bootloader and is mapp
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and store it to
the _instruction address space_ so the CPU can execute it. Boot scenario **1a** uses the processor-internal IMEM
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_Instruction Memory (IMEM)>> as non-initialized
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
true RAM so the bootloader can write the actual executable to it.
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's bus interface.
In this scenario the internal <<_Instruction Memory (IMEM)>> is not implemented at all and the bootloader will write the executable
In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will write the executable
to the processor-external memory.
:sectnums!: