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[RTE] add page fault support

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stnolting 2024-02-01 20:00:41 +01:00
parent 1513d19f38
commit d4d857cdf7
1 changed files with 11 additions and 2 deletions
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13
sw/lib/source/neorv32_rte.c
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@ -187,14 +187,17 @@ static void __attribute__((__naked__,aligned(4))) __neorv32_rte_core(void) {
// find according trap handler base address
uint32_t handler_base;
switch (neorv32_cpu_csr_read(CSR_MCAUSE)) {
case TRAP_CODE_I_PAGE: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_PAGE]; break;
case TRAP_CODE_I_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
case TRAP_CODE_I_ILLEGAL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
case TRAP_CODE_I_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
case TRAP_CODE_BREAKPOINT: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
case TRAP_CODE_L_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_L_MISALIGNED]; break;
case TRAP_CODE_L_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break;
case TRAP_CODE_L_PAGE: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_L_PAGE]; break;
case TRAP_CODE_S_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_S_MISALIGNED]; break;
case TRAP_CODE_S_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
case TRAP_CODE_S_PAGE: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_S_PAGE]; break;
case TRAP_CODE_UENV_CALL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_UENV_CALL]; break;
case TRAP_CODE_MENV_CALL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
case TRAP_CODE_MSI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
@ -347,14 +350,17 @@ static void __neorv32_rte_debug_handler(void) {
// cause
uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
switch (trap_cause) {
case TRAP_CODE_I_PAGE: neorv32_uart0_puts("Instruction page fault"); break;
case TRAP_CODE_I_ACCESS: neorv32_uart0_puts("Instruction access fault"); break;
case TRAP_CODE_I_ILLEGAL: neorv32_uart0_puts("Illegal instruction"); break;
case TRAP_CODE_I_MISALIGNED: neorv32_uart0_puts("Instruction address misaligned"); break;
case TRAP_CODE_BREAKPOINT: neorv32_uart0_puts("Breakpoint"); break;
case TRAP_CODE_BREAKPOINT: neorv32_uart0_puts("Environment breakpoint"); break;
case TRAP_CODE_L_MISALIGNED: neorv32_uart0_puts("Load address misaligned"); break;
case TRAP_CODE_L_ACCESS: neorv32_uart0_puts("Load access fault"); break;
case TRAP_CODE_L_PAGE: neorv32_uart0_puts("Load page fault"); break;
case TRAP_CODE_S_MISALIGNED: neorv32_uart0_puts("Store address misaligned"); break;
case TRAP_CODE_S_ACCESS: neorv32_uart0_puts("Store access fault"); break;
case TRAP_CODE_S_PAGE: neorv32_uart0_puts("Store page fault"); break;
case TRAP_CODE_UENV_CALL: neorv32_uart0_puts("Environment call from U-mode"); break;
case TRAP_CODE_MENV_CALL: neorv32_uart0_puts("Environment call from M-mode"); break;
case TRAP_CODE_MSI: neorv32_uart0_puts("Machine software IRQ"); break;
@ -398,7 +404,7 @@ static void __neorv32_rte_debug_handler(void) {
// halt if fatal exception
if ((trap_cause == TRAP_CODE_I_ACCESS) || (trap_cause == TRAP_CODE_I_MISALIGNED)) {
neorv32_uart0_puts(" !!FATAL EXCEPTION!! Halting CPU. </NEORV32-RTE>\n");
neorv32_uart0_puts(" !!FATAL EXCEPTION!! Halting CPU </NEORV32-RTE>\n");
neorv32_cpu_csr_write(CSR_MIE, 0);
while(1) {
asm volatile ("wfi");
@ -417,14 +423,17 @@ static void __neorv32_rte_debug_handler(void) {
void neorv32_rte_print_info(void) {
const char trap_name[NEORV32_RTE_NUM_TRAPS][13] = {
"I_PAGE ",
"I_ACCESS ",
"I_ILLEGAL ",
"I_MISALIGNED",
"BREAKPOINT ",
"L_MISALIGNED",
"L_ACCESS ",
"L_PAGE ",
"S_MISALIGNED",
"S_ACCESS ",
"S_PAGE ",
"UENV_CALL ",
"MENV_CALL ",
"MSI ",