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added simple fence/fence.i test

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stnolting 2020-07-06 21:46:10 +02:00
parent 4e09225558
commit d4e18558ac
2 changed files with 20 additions and 1 deletions
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19
sw/example/cpu_test/main.c
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@ -196,6 +196,25 @@ int main() {
exception_handler_answer = 0;
// ----------------------------------------------------------
// Test fence instructions - make sure CPU does not crash here and throws no exception
// ----------------------------------------------------------
neorv32_uart_printf("FENCE(.I): ");
cnt_test++;
asm volatile ("fence");
asm volatile ("fence.i");
if (exception_handler_answer != 0) {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
else {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
exception_handler_answer = 0;
// ----------------------------------------------------------
// Unaligned instruction address
// ----------------------------------------------------------

2
sw/lib/include/neorv32.h
View file

@ -134,7 +134,7 @@ enum NEORV32_CPU_MISA_enum {
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension available (r/-) */
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
};