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[docs] remove A ISA, add Zalrsc ISA
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1 changed files with 42 additions and 68 deletions
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@ -49,13 +49,6 @@ will raise an exception to allow a _software-based_ emulation provided by the ap
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access can be **emulated** using the NEORV32 runtime environment. See section <<_application_context_handling>>
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for more information.
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.No Atomic Read-Modify-Write Operations
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[IMPORTANT]
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The NEORV32 <<_a_isa_extension>> only supports the load-reservate (LR) and store-conditional (SR) instructions.
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The remaining read-modify-write operations are not supported. However, these missing instructions can
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be emulated. The NEORV32 <<_core_libraries>> provide an emulation wrapper for the missing AMO/read-modify-write
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instructions that is based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
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<<<
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// ####################################################################################################################
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@ -335,7 +328,7 @@ is driven by the _accessed_ device or bus system (i.e. a processor-internal memo
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| `rw` | 1 | Access direction (`0` = read, `1` = write)
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| `src` | 1 | Access source (`0` = instruction fetch, `1` = load/store)
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| `priv` | 1 | Set if privileged (M-mode) access
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| `rvso` | 1 | Set if current access is a reservation-set operation (atomic `lr` or `sc` instruction)
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| `rvso` | 1 | Set if current access is a reservation-set operation (`lr` or `sc` instruction, <<_zalrsc_isa_extension>>)
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| `fence` | 1 | Data/instruction fence operation; valid without `stb` being set
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|=======================
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@ -382,7 +375,7 @@ additional latency). However, _all_ bus signals (request and response) need to b
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:sectnums:
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==== Atomic Accesses
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The load-reservate (`lr.w`) and store-conditional (`sc.w`) instructions from the <<_a_isa_extension>> execute as standard
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The load-reservate (`lr.w`) and store-conditional (`sc.w`) instructions from the <<_zalrsc_isa_extension>> execute as standard
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load/store bus transactions but with the `rvso` ("reservation set operation") signal being set. It is the task of the
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<<_reservation_set_controller>> to handle these LR/SC bus transactions accordingly. Note that these reservation set operations
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are intended for processor-internal usage only (i.e. the reservation state is not available for processor-external modules yet).
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@ -391,12 +384,6 @@ are intended for processor-internal usage only (i.e. the reservation state is no
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[NOTE]
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See section <<_address_space>> / <<_reservation_set_controller>> for more information.
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.Read-Modify-Write Operations
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[IMPORTANT]
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Read-modify-write operations (like an atomic swap / `amoswap.w`) are **not** supported yet. However, the NEORV32
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<<_core_libraries>> provide an emulation wrapper for those unsupported instructions that is
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based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
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The figure below shows three exemplary bus accesses (1 to 3 from left to right). The `req` signal record represents
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the CPU-side of the bus interface. For easier understanding the current state of the reservation set is added as `rvs_valid` signal.
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@ -417,6 +404,11 @@ image::bus_interface_atomic.png[700]
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[NOTE]
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The "normal" load data mechanism is used to return success/failure of the `sc.w` instruction to the CPU (via the LSB of `rsp.data`).
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.Cache Coherency
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[IMPORTANT]
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Atomic operations **always bypass** the CPU caches using direct/uncached accesses. Care must be taken
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to maintain data cache coherency (e.g. by using the `fence` instruction).
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<<<
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// ####################################################################################################################
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@ -432,7 +424,6 @@ This chapter gives a brief overview of all available ISA extensions.
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[options="header",grid="rows"]
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|=======================
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| Name | Description | <<_processor_top_entity_generics, Enabled by Generic>>
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| <<_a_isa_extension,`A`>> | Atomic memory access instructions | `RISCV_ISA_A`
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| <<_b_isa_extension,`B`>> | Bit manipulation instructions | _Implicitly_ enabled
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| <<_c_isa_extension,`C`>> | Compressed (16-bit) instructions | `RISCV_ISA_C`
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| <<_e_isa_extension,`E`>> | Embedded CPU extension (reduced register file size) | `RISCV_ISA_E`
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@ -440,6 +431,7 @@ This chapter gives a brief overview of all available ISA extensions.
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| <<_m_isa_extension,`M`>> | Integer multiplication and division instructions | `RISCV_ISA_M`
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| <<_u_isa_extension,`U`>> | Less-privileged _user_ mode extension | `RISCV_ISA_U`
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| <<_x_isa_extension,`X`>> | Platform-specific / NEORV32-specific extension | Always enabled
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| <<_zalrsc_isa_extension,`Zalrsc`>> | Atomic reservation-set instructions | `RISCV_ISA_Zalrsc`
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| <<_zba_isa_extension,`Zba`>> | Shifted-add bit manipulation instructions | `RISCV_ISA_Zba`
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| <<_zbb_isa_extension,`Zbb`>> | Basic bit manipulation instructions | `RISCV_ISA_Zbb`
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| <<_zbkb_isa_extension,`Zbkb`>> | Scalar cryptographic bit manipulation instructions | `RISCV_ISA_Zbkb`
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@ -486,56 +478,6 @@ To benchmark a certain processor configuration for its setup-specific CPI value
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`sw/example/performance_tests` test programs.
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==== `A` ISA Extension
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The `A` ISA extension adds instructions and mechanisms for atomic memory access operations. Note that the NEORV32 `A`
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only includes the _load-reservate_ (`lr.w`) and _store-conditional_ (`sc.w`) instructions - the remaining read-modify-write
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instructions (like `amoswap`) are **not supported**. However, these missing instructions can be emulated using the
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LR and SC operations (quote from the RISC-V spec.: "_Any AMO can be emulated by an LR/SC pair._").
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.AMO Emulation
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[NOTE]
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The NEORV32 <<_core_libraries>> provide an emulation wrapper for the missing AMO/read-modify-write instructions that is
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based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
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Atomic instructions allow to notify an application if a certain memory location has been altered by another instance
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(like another process running on the same CPU or a DMA access). Hence, they can be used to implement synchronization
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mechanisms like mutexes and semaphores).
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The NEORV32 `A` extension is enabled via the `RISCV_ISA_A` generic (see <<_processor_top_entity_generics>>).
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When enabled the following additional instructions are available.
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.Instructions and Timing
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[cols="<2,<4,<3"]
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[options="header", grid="rows"]
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|=======================
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| Class | Instructions | Execution cycles
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| Load-reservate word | `lr.w` | 5
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| Store-conditional word | `sc.w` | 5
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|=======================
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The `lr.w` instructions stores one word to a word-aligned address and registers a _reservation set_. The `sc.w`
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instruction stores a word to a word-aligned address only if the reservation set is still valid. Furthermore, the
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`sc.w` operations returns the state of the reservation set (0 = reservation set still valid, data has been written;
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1 = reservation set was broken, no data has been written). The reservation set is invalidated if another `lr.w` instruction
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is executed or if any write access to the _reservated_ address takes place. Traps and/or CPU privilege level changes
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do not modify current reservation sets.
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.`aq` and `rl` Bits
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[NOTE]
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The instruction word's `aq` and `lr` memory ordering bits are not evaluated by the hardware at all.
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.Atomic Memory Access on Hardware Level
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[NOTE]
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More information regarding the atomic memory accesses and the according reservation
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sets can be found in section <<_reservation_set_controller>>.
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.Cache Coherency
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[IMPORTANT]
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Atomic operations **always bypass** the CPU caches using direct/uncached accesses. Care must be taken
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to maintain data cache coherency (e.g. by using the `fence` instruction).
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==== `B` ISA Extension
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The `B` ISA extension adds instructions for bit-manipulation operations.
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@ -657,6 +599,38 @@ RISC-V specs. Also, custom trap codes for <<_mcause>> are implemented.
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* There are <<_neorv32_specific_csrs>>.
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==== `Zalrsc` ISA Extension
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The `Zalrsc` ISA extension is a sub-extension of the RISC-V _atomic memory access_ (`A`) ISA extension and includes
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instructions for reservation-set operations (load-reservate `lr` and store-conditional `sc`) only.
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It is enabled by the top's `RISCV_ISA_Zalrsc` generic.
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.AMO / `A` Emulation
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[NOTE]
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The atomic memory access / read-modify-write operations of the `A` ISA extension can be emulated using the
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LR and SC operations (quote from the RISC-V spec.: "_Any AMO can be emulated by an LR/SC pair._").
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The NEORV32 <<_core_libraries>> provide an emulation wrapper for emulating AMO/read-modify-write instructions that is
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based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`.
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.Instructions and Timing
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[cols="<2,<4,<3"]
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[options="header", grid="rows"]
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|=======================
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| Class | Instructions | Execution cycles
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| Load-reservate word | `lr.w` | 5
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| Store-conditional word | `sc.w` | 5
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|=======================
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.`aq` and `rl` Bits
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[NOTE]
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The instruction word's `aq` and `lr` memory ordering bits are not evaluated by the hardware at all.
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.Atomic Memory Access on Hardware Level
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[NOTE]
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More information regarding the atomic memory accesses and the according reservation
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sets can be found in section <<_reservation_set_controller>>.
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==== `Zifencei` ISA Extension
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The `Zifencei` CPU extension allows manual synchronization of the instruction stream. This extension is always enabled.
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@ -1054,8 +1028,8 @@ behave like regular C functions but that evaluate to a single custom instruction
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.CFU Execution Time
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[NOTE]
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The actual CFU execution time depends on the logic being implemented. The CPU architecture requires a minimal execution
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time of 3 cycle and automatically terminates execution after 512 cycles if the CFU does not complete operation within
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this time window.
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time of 3 cycles (purely combinatorial CFU operation) and automatically terminates execution after 512 cycles if the CFU
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does not complete operation within this time window.
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.Instructions and Timing
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[cols="<2,<5,<2"]
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