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🚀 preparing release v1.11.2

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stnolting 2025-03-15 21:38:47 +01:00
parent ce176bf0a8
commit d8e786b155
4 changed files with 6 additions and 5 deletions
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1
CHANGELOG.md
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 15.03.2025 | [**:rocket:1.11.2**](https://github.com/stnolting/neorv32/releases/tag/v1.11.2) | **New release** | |
| 14.03.2025 | 1.11.1.9 | :bug: fix broken shift instructions of `Zbb` ISA extension (when `Zbkc` and `CPU_FAST_SHIFT_EN` are both disabled) | [#1206](https://github.com/stnolting/neorv32/pull/1206) |
| 02.03.2025 | 1.11.1.8 | :warning: remove DMA FIRQ-triggered auto mode; :warning: remove GPTMR mode configuration bit | [#1194](https://github.com/stnolting/neorv32/pull/1194) |
| 01.03.2025 | 1.11.1.7 | minor rtl / coding style edits (fixing a Vivado 2024.2 synthesis issue) | [#1193](https://github.com/stnolting/neorv32/pull/1193) |

2
docs/attrs.adoc
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@ -2,7 +2,7 @@
:email: stnolting@gmail.com
:keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic
:description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
:revnumber: v1.11.1
:revnumber: v1.11.2
:icons: font
:source-highlighter: highlight.js
:imagesdir: ../figures

6
rtl/core/neorv32_package.vhd
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@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110109"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110200"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width
@ -696,7 +696,7 @@ package neorv32_package is
-- Trap System ----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- exception source bits --
-- exception source list --
constant exc_iaccess_c : natural := 0; -- instruction access fault
constant exc_illegal_c : natural := 1; -- illegal instruction
constant exc_ialign_c : natural := 2; -- instruction address misaligned
@ -709,7 +709,7 @@ package neorv32_package is
constant exc_db_break_c : natural := 9; -- enter debug mode via ebreak instruction
constant exc_db_hw_c : natural := 10; -- enter debug mode via hw trigger
constant exc_width_c : natural := 11; -- length of this list in bits
-- interrupt source bits --
-- interrupt source list --
constant irq_msi_irq_c : natural := 0; -- machine software interrupt
constant irq_mti_irq_c : natural := 1; -- machine timer interrupt
constant irq_mei_irq_c : natural := 2; -- machine external interrupt

2
sw/svd/neorv32.svd
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@ -4,7 +4,7 @@
<vendor>stnolting</vendor>
<name>neorv32</name>
<series>RISC-V</series>
<version>1.11.1</version>
<version>1.11.2</version>
<description>The NEORV32 RISC-V Processor</description>
<!-- CPU core -->