mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-23 21:57:33 -04:00
processor-specific information is now obtained from the SYSINFO IO module
This commit is contained in:
stnolting
parent
8ae891352a
commit
da5b86463c
12 changed files with 105 additions and 75 deletions
|
|
@ -73,28 +73,21 @@ enum NEORV32_CPU_CSRS_enum {
|
|||
|
||||
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
|
||||
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
|
||||
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */
|
||||
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
|
||||
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word - only 20-bit wide!*/
|
||||
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word - only 20-bit wide! */
|
||||
|
||||
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
|
||||
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */
|
||||
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
|
||||
|
||||
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */
|
||||
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) - only 20-bit wide! */
|
||||
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */
|
||||
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
|
||||
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) - only 20-bit wide! */
|
||||
|
||||
CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
|
||||
CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
|
||||
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
|
||||
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
|
||||
|
||||
CSR_MFEATURES = 0xfc0, /**< 0xfc0 - CUSTOM (r/-): Implemented processor devices/features (via IO_x_USE generics) */
|
||||
CSR_MCLOCK = 0xfc1, /**< 0xfc1 - CUSTOM (r/-): Processor primary clock spedd in Hz (via CLOCK_FREQUENCY generic)*/
|
||||
CSR_MISPACEBASE = 0xfc4, /**< 0xfc4 - CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */
|
||||
CSR_MDSPACEBASE = 0xfc5, /**< 0xfc5 - CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */
|
||||
CSR_MISPACESIZE = 0xfc6, /**< 0xfc6 - CUSTOM (r/-): Total size of instruction memory space in byte (via MEM_ISPACE_SIZE generic) */
|
||||
CSR_MDSPACESIZE = 0xfc7 /**< 0xfc7 - CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */
|
||||
CSR_MHARTID = 0xf14 /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -142,30 +135,6 @@ enum NEORV32_CPU_MISA_enum {
|
|||
};
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* CPU <b>mfeatures</b> CSR (r/-): Implemented processor devices/features (CUSTOM)
|
||||
**************************************************************************/
|
||||
enum NEORV32_CPU_MFEATURES_enum {
|
||||
CPU_MFEATURES_BOOTLOADER = 0, /**< CPU mfeatures CSR (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
|
||||
CPU_MFEATURES_MEM_EXT = 1, /**< CPU mfeatures CSR (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
|
||||
CPU_MFEATURES_MEM_INT_IMEM = 2, /**< CPU mfeatures CSR (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
|
||||
CPU_MFEATURES_MEM_INT_IMEM_ROM = 3, /**< CPU mfeatures CSR (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
|
||||
CPU_MFEATURES_MEM_INT_DMEM = 4, /**< CPU mfeatures CSR (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
|
||||
CPU_MFEATURES_CSR_COUNTERS = 5, /**< CPU mfeatures CSR (5) (r/-): RISC-V performance counters implemented when 1 (via CSR_COUNTERS_USE generic) */
|
||||
|
||||
CPU_MFEATURES_IO_GPIO = 16, /**< CPU mfeatures CSR (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
|
||||
CPU_MFEATURES_IO_MTIME = 17, /**< CPU mfeatures CSR (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
|
||||
CPU_MFEATURES_IO_UART = 18, /**< CPU mfeatures CSR (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
|
||||
CPU_MFEATURES_IO_SPI = 19, /**< CPU mfeatures CSR (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
|
||||
CPU_MFEATURES_IO_TWI = 20, /**< CPU mfeatures CSR (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */
|
||||
CPU_MFEATURES_IO_PWM = 21, /**< CPU mfeatures CSR (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
|
||||
CPU_MFEATURES_IO_WDT = 22, /**< CPU mfeatures CSR (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
|
||||
CPU_MFEATURES_IO_CLIC = 23, /**< CPU mfeatures CSR (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */
|
||||
CPU_MFEATURES_IO_TRNG = 24, /**< CPU mfeatures CSR (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
|
||||
CPU_MFEATURES_IO_DEVNULL = 25 /**< CPU mfeatures CSR (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
|
||||
};
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Exception IDs.
|
||||
**************************************************************************/
|
||||
|
|
@ -185,6 +154,25 @@ enum NEORV32_EXCEPTION_IDS_enum {
|
|||
};
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Exception codes from mcause CSR.
|
||||
**************************************************************************/
|
||||
enum NEORV32_EXCEPTION_CODES_enum {
|
||||
EXCCODE_I_MISALIGNED = 0x00000000, /**< 0: Instruction address misaligned */
|
||||
EXCCODE_I_ACCESS = 0x00000001, /**< 1: Instruction (bus) access fault */
|
||||
EXCCODE_I_ILLEGAL = 0x00000002, /**< 2: Illegal instruction */
|
||||
EXCCODE_BREAKPOINT = 0x00000003, /**< 3: Breakpoint (EBREAK instruction) */
|
||||
EXCCODE_L_MISALIGNED = 0x00000004, /**< 4: Load address misaligned */
|
||||
EXCCODE_L_ACCESS = 0x00000005, /**< 5: Load (bus) access fault */
|
||||
EXCCODE_S_MISALIGNED = 0x00000006, /**< 6: Store address misaligned */
|
||||
EXCCODE_S_ACCESS = 0x00000007, /**< 7: Store (bus) access fault */
|
||||
EXCCODE_MENV_CALL = 0x0000000b, /**< 11: Environment call from machine mode (ECALL instruction) */
|
||||
EXCCODE_MSI = 0x80000003, /**< 16 + 3: Machine software interrupt */
|
||||
EXCCODE_MTI = 0x80000007, /**< 16 + 7: Machine timer interrupt (via MTIME) */
|
||||
EXCCODE_MEI = 0x8000000b /**< 16 + 11: Machine external interrupt (via CLIC) */
|
||||
};
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* Processor clock prescalers
|
||||
**************************************************************************/
|
||||
|
|
@ -514,10 +502,56 @@ enum NEORV32_TRNG_DUTY_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** DEVNULL data register (r/w) */
|
||||
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFCUL))
|
||||
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFC8UL))
|
||||
/**@}*/
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* @name IO Device: System Configuration Info Memory (SYSINFO)
|
||||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** SYSINFO(0): Clock speed */
|
||||
#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
|
||||
/** SYSINFO(1): reserved */
|
||||
#define SYSINFO_reserved0 (*(IO_ROM32 0xFFFFFFE4UL))
|
||||
/** SYSINFO(2): Clock speed */
|
||||
#define SYSINFO_FEATURES (*(IO_ROM32 0xFFFFFFE8UL))
|
||||
/** SYSINFO(3): reserved */
|
||||
#define SYSINFO_reserved1 (*(IO_ROM32 0xFFFFFFECUL))
|
||||
/** SYSINFO(4): Instruction memory address space base */
|
||||
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
|
||||
/** SYSINFO(5): Data memory address space base */
|
||||
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
|
||||
/** SYSINFO(6): Instruction memory address space size in bytes */
|
||||
#define SYSINFO_ISPACE_SIZE (*(IO_ROM32 0xFFFFFFF8UL))
|
||||
/** SYSINFO(7): Data memory address space size in bytes */
|
||||
#define SYSINFO_DSPACE_SIZE (*(IO_ROM32 0xFFFFFFFCUL))
|
||||
/**@}*/
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* SYSINFO_FEATURES (r/-): Implemented processor devices/features
|
||||
**************************************************************************/
|
||||
enum NEORV32_SYSINFO_FEATURES_enum {
|
||||
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
|
||||
SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
|
||||
SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
|
||||
SYSINFO_FEATURES_MEM_INT_IMEM_ROM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
|
||||
SYSINFO_FEATURES_MEM_INT_DMEM = 4, /**< SYSINFO_FEATURES (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
|
||||
|
||||
SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
|
||||
SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
|
||||
SYSINFO_FEATURES_IO_UART = 18, /**< SYSINFO_FEATURES (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
|
||||
SYSINFO_FEATURES_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
|
||||
SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */
|
||||
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
|
||||
SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
|
||||
SYSINFO_FEATURES_IO_CLIC = 23, /**< SYSINFO_FEATURES (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */
|
||||
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
|
||||
SYSINFO_FEATURES_IO_DEVNULL = 25 /**< SYSINFO_FEATURES (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
|
||||
};
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Include all IO driver headers
|
||||
// ----------------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ static uint32_t __neorv32_clic_vectors[8] __attribute__((unused));
|
|||
**************************************************************************/
|
||||
int neorv32_clic_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_CLIC)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_CLIC)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -221,7 +221,7 @@ uint64_t neorv32_cpu_get_systime(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_cpu_delay_ms(uint32_t time_ms) {
|
||||
|
||||
uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000
|
||||
uint32_t clock_speed = SYSINFO_CLK >> 10; // fake divide by 1000
|
||||
clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
|
||||
uint32_t cnt = clock_speed * time_ms;
|
||||
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
**************************************************************************/
|
||||
int neorv32_gpio_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_GPIO)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_GPIO)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
**************************************************************************/
|
||||
int neorv32_mtime_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_MTIME)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_MTIME)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
**************************************************************************/
|
||||
int neorv32_pwm_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_PWM)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_PWM)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)) {
|
|||
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt
|
||||
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt
|
||||
|
||||
uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table
|
||||
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table
|
||||
vt_base = vt_base + (((uint32_t)exc_id) << 2);
|
||||
(*(IO_REG32 (vt_base))) = (uint32_t)handler;
|
||||
|
||||
|
|
@ -126,7 +126,7 @@ int neorv32_rte_exception_uninstall(uint8_t exc_id) {
|
|||
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt
|
||||
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt
|
||||
|
||||
uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table
|
||||
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table
|
||||
vt_base = vt_base + (((uint32_t)exc_id) << 2);
|
||||
(*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered
|
||||
|
||||
|
|
@ -259,69 +259,65 @@ void neorv32_rte_print_hw_config(void) {
|
|||
}
|
||||
neorv32_uart_printf("(0x%x)\n", tmp);
|
||||
|
||||
// Performance counters
|
||||
neorv32_uart_printf("CNT & time CSRs: ");
|
||||
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS));
|
||||
|
||||
// Clock speed
|
||||
neorv32_uart_printf("Clock speed: %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK));
|
||||
neorv32_uart_printf("Clock speed: %u Hz\n", SYSINFO_CLK);
|
||||
|
||||
// Memory configuration
|
||||
neorv32_uart_printf("\n-- Memory Configuration --\n");
|
||||
|
||||
uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE);
|
||||
uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE);
|
||||
uint32_t size = SYSINFO_ISPACE_SIZE;
|
||||
uint32_t base = SYSINFO_ISPACE_BASE;
|
||||
neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
|
||||
neorv32_uart_printf("Internal IMEM: ");
|
||||
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM));
|
||||
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM));
|
||||
neorv32_uart_printf("Internal IMEM as ROM: ");
|
||||
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM));
|
||||
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
|
||||
|
||||
size = neorv32_cpu_csr_read(CSR_MDSPACESIZE);
|
||||
base = neorv32_cpu_csr_read(CSR_MDSPACEBASE);
|
||||
size = SYSINFO_DSPACE_SIZE;
|
||||
base = SYSINFO_DSPACE_BASE;
|
||||
neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base);
|
||||
neorv32_uart_printf("Internal DMEM: ");
|
||||
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM));
|
||||
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
|
||||
|
||||
neorv32_uart_printf("Bootloader: ");
|
||||
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER));
|
||||
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
|
||||
|
||||
neorv32_uart_printf("External interface: ");
|
||||
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT));
|
||||
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
|
||||
|
||||
// peripherals
|
||||
neorv32_uart_printf("\n-- Peripherals --\n");
|
||||
tmp = neorv32_cpu_csr_read(CSR_MFEATURES);
|
||||
tmp = SYSINFO_FEATURES;
|
||||
|
||||
neorv32_uart_printf("GPIO: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
|
||||
|
||||
neorv32_uart_printf("MTIME: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
|
||||
|
||||
neorv32_uart_printf("UART: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART));
|
||||
|
||||
neorv32_uart_printf("SPI: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
|
||||
|
||||
neorv32_uart_printf("TWI: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
|
||||
|
||||
neorv32_uart_printf("PWM: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
|
||||
|
||||
neorv32_uart_printf("WDT: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
|
||||
|
||||
neorv32_uart_printf("CLIC: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CLIC));
|
||||
|
||||
neorv32_uart_printf("TRNG: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
|
||||
|
||||
neorv32_uart_printf("DEVNULL: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
**************************************************************************/
|
||||
int neorv32_spi_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_SPI)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_SPI)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
**************************************************************************/
|
||||
int neorv32_trng_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_TRNG)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_TRNG)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
**************************************************************************/
|
||||
int neorv32_twi_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_TWI)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_TWI)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static void __neorv32_uart_tohex(uint32_t x, char *res) __attribute__((unused));
|
|||
**************************************************************************/
|
||||
int neorv32_uart_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_UART)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_UART)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
@ -80,7 +80,7 @@ void neorv32_uart_setup(uint32_t baudrate, uint8_t rx_irq, uint8_t tx_irq) {
|
|||
UART_CT = 0; // reset
|
||||
|
||||
// raw baud rate prescaler
|
||||
uint32_t clock = neorv32_cpu_csr_read(CSR_MCLOCK);
|
||||
uint32_t clock = SYSINFO_CLK;
|
||||
uint16_t i = 0; // BAUD rate divisor
|
||||
uint8_t p = 0; // prsc = CLK/2
|
||||
while (clock >= 2*baudrate) {
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
**************************************************************************/
|
||||
int neorv32_wdt_available(void) {
|
||||
|
||||
if (neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_IO_WDT)) {
|
||||
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_WDT)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue