[docs] minor edits

README.md

@@ -84,7 +84,7 @@ The processor passes the official RISC-V architecture tests to ensure compatibil
 [neorv32-riscof](https://github.com/stnolting/neorv32-riscof) repository. It can successfully run _any_ C program
 (for example from the [`sw/example`](https://github.com/stnolting/neorv32/tree/main/sw/example) folder) including CoreMark
 and FreeRTOS and can be synthesized for _any_ target technology - [tested](https://github.com/stnolting/neorv32-setups)
-on Intel, AMD and Lattice FPGAs. The conversion into a plain-Verilog netlist module is automatically checked by the
+on Intel, AMD and Lattice FPGAs. The conversion into a single, plain-Verilog module file is automatically checked by the
 [neorv32-verilog](https://github.com/stnolting/neorv32-verilog) repository.
 
 

docs/datasheet/overview.adoc

@@ -63,7 +63,7 @@ include::rationale.adoc[]
 
 * all-in-one package: **CPU** + **SoC** + **Software Framework & Tooling**
 * completely described in behavioral, platform-independent VHDL - no vendor- or technology-specific primitives, attributes, macros, libraries, etc. are used at all
-* all-Verilog "version" available (auto-generated netlist)
+* all-Verilog "version" available (auto-generated by GHDL)
 * extensive configuration options for adapting the processor to the requirements of the application
 * highly extensible hardware - on CPU, SoC and system level
 * aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off

docs/userguide/litex_support.adoc

@@ -37,7 +37,7 @@ LiteX: external interrupt - the "RISC-V machine external interrupt" is not suppo
 You can download prebuilt packages for example from https://github.com/YosysHQ/fpga-toolchain, which is _no longer maintained. It is superdesed
 by https://github.com/YosysHQ/fpga-toolchain.
 . _EXPERIMENTAL:_ GHDL provides a https://ghdl.github.io/ghdl/using/Synthesis.html[synthesis options], which converts a VHDL setup into a plain-Verilog
-netlist module (not tested on LiteX yet). Check out https://github.com/stnolting/neorv32-verilog[neorv32-verilog] for more information.
+module (not tested on LiteX yet). Check out https://github.com/stnolting/neorv32-verilog[neorv32-verilog] for more information.
 
 
 .GHDL-yosys Plugin
@@ -161,7 +161,7 @@ mem_read                 - Read address space
 mem_list                 - List available memory regions
 
 
-litex> 
+litex>
 ----
 
 You can use the provided console to execute LiteX commands.

docs/userguide/neorv32_in_verilog.adoc

@@ -3,22 +3,23 @@
 == NEORV32 in Verilog
 
 If you are more of a Verilog fan or if your EDA toolchain does not support VHDL or mixed-language designs
-you can use an **all-Verilog** version of the processor provided by the https://github.com/stnolting/neorv32-verilog[`neorv32-verilog`] repository.
+you can use an **all-Verilog** version of the processor provided by the
+https://github.com/stnolting/neorv32-verilog[`neorv32-verilog`] repository.
 
 [IMPORTANT]
 Note that this is **not a manual re-implementation of the core in Verilog** but rather an automated conversion.
 
 GHDL's synthesis feature is used to convert a pre-configured NEORV32 setup - including all peripherals, memories
-and memory images - into an unoptimized plain-Verilog netlist module file without any (technology-specific) primitives.
+and memory images - into a single, unoptimized plain-Verilog module file without any (technology-specific) primitives.
 
 .GHDL Synthesis
 [TIP]
 More information regarding GHDL's synthesis option can be found at https://ghdl.github.io/ghdl/using/Synthesis.html.
 
-An intermediate VHDL wrapper is provided that can be used to configure the processor (using VHDL generics) and to customize
-the interface ports. After conversion, a single Verilog file is generated that contains the whole NEORV32 processor.
-The original processor module hierarchy is preserved as well as most (all?) signal names, which allows easy inspection and debugging
-of simulation waveforms and synthesis results.
+An intermediate VHDL wrapper is provided that can be used to configure the processor (using VHDL generics) and to
+customize the interface ports. After conversion, a single Verilog file is generated that contains the whole NEORV32
+processor. The original processor module hierarchy is preserved as well as most (all?) signal names, which allows
+easy inspection and debugging of simulation waveforms and synthesis results.
 
 .Example: interface of the resulting NEORV32 Verilog module (for a minimal SoC configuration)
 [source,verilog]
@@ -30,7 +31,7 @@ module neorv32_verilog_wrapper
    output uart0_txd_o);
 ----
 
-The generated Verilog netlist has been tested with
+The generated Verilog code has been simulated and verified with
 https://github.com/steveicarus/iverilog[Icarus Verilog]
 (simulation) and AMD Vivado (simulation and synthesis).