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[docs] test wavedrom inlining

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stnolting 2025-03-16 07:50:41 +01:00
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25
docs/datasheet/cpu_cfu.adoc
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@ -65,7 +65,17 @@ always compile-time-static.
Example operation: `rd <= rs1 xnor rs2` (bit-wise logical XNOR)
.CFU R3-type instruction format
image::cfu_r3type_instruction.png[align=left]
[wavedrom, png]
----
{reg: [
{bits: 7, name: 11, attr: 'Opcode: Custom-0'},
{bits: 5, name: 'rd', attr: 'Destination'},
{bits: 3, name: 'funct3', type: 1},
{bits: 5, name: 'rs1', attr: 'Source 1'},
{bits: 5, name: 'rs2', attr: 'Source 2'},
{bits: 7, name: 'funct7', type: 1}
]}
----
* `funct7`: 7-bit immediate (immediate data or function select)
* `rs2`: address of second source register (providing 32-bit source data)
@ -92,7 +102,18 @@ values are always compile-time-static.
Example operation: `rd <= (rs1 * rs2 + rs3)[31:0]` (multiply-and-accumulate; "MAC")
.CFU R4-type instruction format
image::cfu_r4type_instruction.png[align=left]
[wavedrom, png]
----
{reg: [
{bits: 7, name: 43, attr: 'Opcode: Custom-1'},
{bits: 5, name: 'rd', attr: 'Destination'},
{bits: 3, name: 'funct3', type: 1},
{bits: 5, name: 'rs1', attr: 'Source 1'},
{bits: 5, name: 'rs2', attr: 'Source 2'},
{bits: 2, name: 4, attr: '-'},
{bits: 5, name: 'rs3', attr: 'Source 3'}
]}
----
* `rs3`: address of third source register (providing 32-bit source data)
* `rs2`: address of second source register (providing 32-bit source data)