[sw/lib] minor comment fix

sw/lib/include/neorv32_cfs.h

@@ -29,7 +29,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t REG[(64*1024)/4]; /**< CFS registers, user-defined */
 } neorv32_cfs_t;
 
-/** CFS module hardware access (#neorv32_cfs_t) */
+/** CFS module hardware handle (#neorv32_cfs_t) */
 #define NEORV32_CFS ((neorv32_cfs_t*) (NEORV32_CFS_BASE))
 /**@}*/
 

sw/lib/include/neorv32_clint.h

@@ -28,7 +28,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   subwords64_t MTIME;          /**< global machine timer; 64-bit */
 } neorv32_clint_t;
 
-/** CLINT module hardware access (#neorv32_clint_t) */
+/** CLINT module hardware handle (#neorv32_clint_t) */
 #define NEORV32_CLINT ((neorv32_clint_t*) (NEORV32_CLINT_BASE))
 /**@}*/
 

sw/lib/include/neorv32_crc.h

@@ -29,7 +29,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t SREG; /**< offset 12: CRC shift register */
 } neorv32_crc_t;
 
-/** CRC module hardware access (#neorv32_crc_t) */
+/** CRC module hardware handle (#neorv32_crc_t) */
 #define NEORV32_CRC ((neorv32_crc_t*) (NEORV32_CRC_BASE))
 
 /** CRC mode select */

sw/lib/include/neorv32_dma.h

@@ -29,7 +29,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t TTYPE;    /**< offset 12: transfer type configuration register & manual trigger (#NEORV32_DMA_TTYPE_enum) */
 } neorv32_dma_t;
 
-/** DMA module hardware access (#neorv32_dma_t) */
+/** DMA module hardware handle (#neorv32_dma_t) */
 #define NEORV32_DMA ((neorv32_dma_t*) (NEORV32_DMA_BASE))
 
 /** DMA control and status register bits */

sw/lib/include/neorv32_gpio.h

@@ -32,7 +32,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t       IRQ_PENDING;  /**< interrupt pending */
 } neorv32_gpio_t;
 
-/** GPIO module hardware access (#neorv32_gpio_t) */
+/** GPIO module hardware handle (#neorv32_gpio_t) */
 #define NEORV32_GPIO ((neorv32_gpio_t*) (NEORV32_GPIO_BASE))
 /**@}*/
 

sw/lib/include/neorv32_gptmr.h

@@ -28,7 +28,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   const uint32_t COUNT; /**< offset 8: counter register, read-only */
 } neorv32_gptmr_t;
 
-/** GPTMR module hardware access (#neorv32_gptmr_t) */
+/** GPTMR module hardware handle (#neorv32_gptmr_t) */
 #define NEORV32_GPTMR ((neorv32_gptmr_t*) (NEORV32_GPTMR_BASE))
 
 /** GPTMR control register bits */

sw/lib/include/neorv32_neoled.h

@@ -27,7 +27,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */
 } neorv32_neoled_t;
 
-/** NEOLED module hardware access (#neorv32_neoled_t) */
+/** NEOLED module hardware handle (#neorv32_neoled_t) */
 #define NEORV32_NEOLED ((neorv32_neoled_t*) (NEORV32_NEOLED_BASE))
 
 /** NEOLED control register bits */

sw/lib/include/neorv32_onewire.h

@@ -27,7 +27,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t DCMD; /**< offset 4: command and data register (#NEORV32_ONEWIRE_DCMD_enum) */
 } neorv32_onewire_t;
 
-/** ONEWIRE module hardware access (#neorv32_onewire_t) */
+/** ONEWIRE module hardware handle (#neorv32_onewire_t) */
 #define NEORV32_ONEWIRE ((neorv32_onewire_t*) (NEORV32_ONEWIRE_BASE))
 
 /** ONEWIRE control register bits */

sw/lib/include/neorv32_pwm.h

@@ -26,7 +26,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t CHANNEL_CFG[16]; /**< offset 0..64: channel configuration 0..15 (#CHANNEL_CFG_enum) */
 } neorv32_pwm_t;
 
-/** PWM module hardware access (#neorv32_pwm_t) */
+/** PWM module hardware handle (#neorv32_pwm_t) */
 #define NEORV32_PWM ((neorv32_pwm_t*) (NEORV32_PWM_BASE))
 
 /** PWM channel configuration bits */

sw/lib/include/neorv32_sdi.h

@@ -27,7 +27,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t DATA; /**< offset 4: data register */
 } neorv32_sdi_t;
 
-/** SDI module hardware access (#neorv32_sdi_t) */
+/** SDI module hardware handle (#neorv32_sdi_t) */
 #define NEORV32_SDI ((neorv32_sdi_t*) (NEORV32_SDI_BASE))
 
 /** SDI control register bits */

sw/lib/include/neorv32_slink.h

@@ -29,7 +29,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t DATA_LAST; /**< offset 12: RX/TX data register (+ TX end-of-stream) */
 } neorv32_slink_t;
 
-/** SLINK module hardware access (#neorv32_slink_t) */
+/** SLINK module hardware handle (#neorv32_slink_t) */
 #define NEORV32_SLINK ((neorv32_slink_t*) (NEORV32_SLINK_BASE))
 
 /** SLINK control register bits */

sw/lib/include/neorv32_spi.h

@@ -27,7 +27,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t DATA;  /**< offset 4: data register  (#NEORV32_SPI_DATA_enum) */
 } neorv32_spi_t;
 
-/** SPI module hardware access (#neorv32_spi_t) */
+/** SPI module hardware handle (#neorv32_spi_t) */
 #define NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE))
 
 /** SPI control register bits */

sw/lib/include/neorv32_trng.h

@@ -27,7 +27,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   const uint32_t DATA; /**< offset 4: random data register (#NEORV32_TRNG_DATA_enum) */
 } neorv32_trng_t;
 
-/** TRNG module hardware access (#neorv32_trng_t) */
+/** TRNG module hardware handle (#neorv32_trng_t) */
 #define NEORV32_TRNG ((neorv32_trng_t*) (NEORV32_TRNG_BASE))
 
 /** TRNG control register bits */

sw/lib/include/neorv32_twd.h

@@ -27,7 +27,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t DATA; /**< offset 4: data register (#NEORV32_TWD_DATA_enum) */
 } neorv32_twd_t;
 
-/** TWD module hardware access (#neorv32_twd_t) */
+/** TWD module hardware handle (#neorv32_twd_t) */
 #define NEORV32_TWD ((neorv32_twd_t*) (NEORV32_TWD_BASE))
 
 /** TWD control register bits */

sw/lib/include/neorv32_twi.h

@@ -27,7 +27,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t DCMD; /**< offset 4: data/cmd register (#NEORV32_TWI_DCMD_enum) */
 } neorv32_twi_t;
 
-/** TWI module hardware access (#neorv32_twi_t) */
+/** TWI module hardware handle (#neorv32_twi_t) */
 #define NEORV32_TWI ((neorv32_twi_t*) (NEORV32_TWI_BASE))
 
 /** TWI control register bits */

sw/lib/include/neorv32_uart.h

@@ -28,10 +28,10 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t DATA;  /**< offset 4: data register  (#NEORV32_UART_DATA_enum) */
 } neorv32_uart_t;
 
-/** UART0 module hardware access (#neorv32_uart_t) */
+/** UART0 module hardware handle (#neorv32_uart_t) */
 #define NEORV32_UART0 ((neorv32_uart_t*) (NEORV32_UART0_BASE))
 
-/** UART1 module hardware access (#neorv32_uart_t) */
+/** UART1 module hardware handle (#neorv32_uart_t) */
 #define NEORV32_UART1 ((neorv32_uart_t*) (NEORV32_UART1_BASE))
 
 /** UART control register bits */

sw/lib/include/neorv32_wdt.h

@@ -27,7 +27,7 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
   uint32_t RESET; /**< offset 4: WDT reset trigger (write password to "feed" watchdog) */
 } neorv32_wdt_t;
 
-/** WDT module hardware access (#neorv32_wdt_t) */
+/** WDT module hardware handle (#neorv32_wdt_t) */
 #define NEORV32_WDT ((neorv32_wdt_t*) (NEORV32_WDT_BASE))
 
 /** WDT control register bits */