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stnolting 2024-10-05 16:03:26 +02:00 • committed by GitHub
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7
.github/workflows/Documentation.yml vendored
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@ -1,13 +1,16 @@
name: 'Documentation'
name: Documentation
on:
push:
paths:
- 'docs/**'
pull_request:
paths:
- 'docs/**'
workflow_dispatch:
jobs:
doxygen:
runs-on: ubuntu-latest
name: 'SW Framework'

7
.github/workflows/Processor.yml vendored
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@ -3,25 +3,18 @@ name: Processor
on:
push:
branches:
- main
paths:
- 'rtl/**'
- 'sw/**'
- 'sim/**'
- '.github/workflows/**'
pull_request:
branches:
- main
paths:
- 'rtl/**'
- 'sw/**'
- 'sim/**'
- '.github/workflows/**'
workflow_dispatch:
jobs:
Software:
runs-on: ubuntu-latest

1
CHANGELOG.md
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 05.10.2024 | 1.10.5.3 | upgrade neoTRNG to version 3.2 | [#1048](https://github.com/stnolting/neorv32/pull/1048) |
| 03.10.2024 | 1.10.5.2 | :warning: remove `A` ISA extensions; replaced by new `Zalrsc` ISA extension | [#1047](https://github.com/stnolting/neorv32/pull/1047) |
| 02.10.2024 | 1.10.5.1 | :warning: rework CFU interface; reduce minimal latency of CFU instructions from 4 cycles to 3 cycles | [#1046](https://github.com/stnolting/neorv32/pull/1046) |
| 01.10.2024 | [**:rocket:1.10.5**](https://github.com/stnolting/neorv32/releases/tag/v1.10.5) | **New release** | |

2
rtl/core/neorv32_cpu_lsu.vhd
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@ -108,7 +108,7 @@ begin
dbus_req_o.fence <= ctrl_i.lsu_fence; -- this is valid without STB being set
-- Data Input Alignment and Sign-Extension ------------------------------------------------
-- Data Input: Alignment and Sign-Extension -----------------------------------------------
-- -------------------------------------------------------------------------------------------
mem_di_reg: process(rstn_i, clk_i)
begin

2
rtl/core/neorv32_package.vhd
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@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100502"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100503"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

2
rtl/core/neorv32_top.vhd
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@ -498,7 +498,7 @@ begin
port map (
-- global control --
clk_i => clk_cpu, -- switchable clock
clk_aux_i => clk_i,
clk_aux_i => clk_i, -- always-on clock
rstn_i => rstn_sys,
sleep_o => cpu_sleep,
debug_o => cpu_debug,

60
rtl/core/neorv32_trng.vhd
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@ -53,16 +53,16 @@ architecture neorv32_trng_rtl of neorv32_trng is
-- neoTRNG true random number generator --
component neoTRNG
generic (
NUM_CELLS : natural := 3; -- number of ring-oscillator cells
NUM_INV_START : natural := 5; -- number of inverters in first cell, has to be odd, min 3
NUM_CELLS : natural range 1 to 99 := 3; -- number of ring-oscillator cells
NUM_INV_START : natural range 3 to 99 := 5; -- number of inverters in first cell, has to be odd, min 3
SIM_MODE : boolean := false -- enable simulation mode (adding explicit propagation delay)
);
port (
clk_i : in std_ulogic; -- module clock
rstn_i : in std_ulogic; -- module reset, low-active, async, optional
enable_i : in std_ulogic; -- module enable (high-active)
data_o : out std_ulogic_vector(7 downto 0); -- random data byte output
valid_o : out std_ulogic -- data_o is valid when set
valid_o : out std_ulogic; -- data_o is valid when set
data_o : out std_ulogic_vector(7 downto 0) -- random data byte output
);
end component;
@ -132,8 +132,8 @@ begin
clk_i => clk_i,
rstn_i => rstn_i,
enable_i => enable,
data_o => fifo.wdata,
valid_o => fifo.we
valid_o => fifo.we,
data_o => fifo.wdata
);
@ -189,7 +189,7 @@ end neorv32_trng_rtl;
-- #################################################################################################
-- # neoTRNG - A Tiny and Platform-Independent True Random Number Generator (version 3.1) #
-- # neoTRNG - A Tiny and Platform-Independent True Random Number Generator (Version 3.2) #
-- # https://github.com/stnolting/neoTRNG #
-- # ********************************************************************************************* #
-- # The neoTNG true-random number generator samples free-running ring-oscillators (combinatorial #
@ -241,26 +241,26 @@ use ieee.numeric_std.all;
entity neoTRNG is
generic (
NUM_CELLS : natural := 3; -- number of ring-oscillator cells
NUM_INV_START : natural := 5; -- number of inverters in first ring-oscillator cell, has to be odd
SIM_MODE : boolean := false -- enable simulation mode (adding explicit propagation delay)
NUM_CELLS : natural range 1 to 99 := 3; -- number of ring-oscillator cells
NUM_INV_START : natural range 3 to 99 := 5; -- number of inverters in first ring-oscillator cell, has to be odd
SIM_MODE : boolean := false -- enable simulation mode (no physical random if enabled!)
);
port (
clk_i : in std_ulogic; -- module clock
rstn_i : in std_ulogic; -- module reset, low-active, async, optional
enable_i : in std_ulogic; -- module enable (high-active)
data_o : out std_ulogic_vector(7 downto 0); -- random data byte output
valid_o : out std_ulogic -- data_o is valid when set
valid_o : out std_ulogic; -- data_o is valid when set (high for one cycle)
data_o : out std_ulogic_vector(7 downto 0) -- random data byte output
);
end neoTRNG;
architecture neoTRNG_rtl of neoTRNG is
-- entropy generator cell --
-- entropy source cell --
component neoTRNG_cell
generic (
NUM_INV : natural := 3; -- number of inverters, has to be odd, min 3
SIM_MODE : boolean := false -- enable simulation mode (adding explicit propagation delay)
NUM_INV : natural range 3 to 999 := 3; -- number of inverters, has to be odd, min 3
SIM_MODE : boolean := false -- enable simulation mode (no physical random if enabled!)
);
port (
clk_i : in std_ulogic; -- clock
@ -275,7 +275,7 @@ architecture neoTRNG_rtl of neoTRNG is
signal cell_en_in : std_ulogic_vector(NUM_CELLS-1 downto 0); -- enable-sreg input
signal cell_en_out : std_ulogic_vector(NUM_CELLS-1 downto 0); -- enable-sreg output
signal cell_rnd : std_ulogic_vector(NUM_CELLS-1 downto 0); -- cell random output
signal rnd_raw : std_ulogic; -- combined raw random data
signal cell_sum : std_ulogic; -- combined random data
-- de-biasing --
signal debias_sreg : std_ulogic_vector(1 downto 0); -- sample buffer
@ -293,20 +293,17 @@ begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report
"[neoTRNG] The neoTRNG (v3.1) - A Tiny and Platform-Independent True Random Number Generator, " &
"[neoTRNG] The neoTRNG (v3.2) - A Tiny and Platform-Independent True Random Number Generator, " &
"https://github.com/stnolting/neoTRNG" severity note;
assert (NUM_INV_START mod 2) /= 0 report
"[neoTRNG] Number of inverters in first cell <NUM_INV_START> has to be odd!" severity error;
assert NUM_INV_START >= 3 report
"[neoTRNG] Number of inverters in first cell <NUM_INV_START> has to be at least 3!" severity error;
assert not SIM_MODE report
"[neoTRNG] Simulation-mode enabled!" severity warning;
"[neoTRNG] Simulation-mode enabled (NO TRUE/PHYSICAL RANDOM)!" severity warning;
-- Entropy Source(s) ----------------------------------------------------------------------
-- Entropy Source -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
entropy_cell_gen:
for i in 0 to NUM_CELLS-1 generate
@ -336,7 +333,7 @@ begin
for i in 0 to NUM_CELLS-1 loop
tmp_v := tmp_v xor cell_rnd(i);
end loop;
rnd_raw <= tmp_v;
cell_sum <= tmp_v;
end process combine;
@ -348,7 +345,7 @@ begin
debias_sreg <= (others => '0');
debias_state <= '0';
elsif rising_edge(clk_i) then
debias_sreg <= debias_sreg(0) & rnd_raw;
debias_sreg <= debias_sreg(0) & cell_sum;
-- start operation when last cell is enabled and process in every second cycle --
debias_state <= (not debias_state) and cell_en_out(cell_en_out'left);
end if;
@ -385,11 +382,10 @@ begin
end neoTRNG_rtl;
-- **********************************************************************************************************
-- neoTRNG entropy source cell, based on a simple ring-oscillator constructed from an odd number
-- of inverter. The inverters are decoupled using individually-enabled latches to prevent synthesis
-- from removing parts of the oscillator chain.
-- from "optimizing" (=removing) parts of the oscillator chain.
-- **********************************************************************************************************
library ieee;
@ -397,8 +393,8 @@ use ieee.std_logic_1164.all;
entity neoTRNG_cell is
generic (
NUM_INV : natural := 3; -- number of inverters, has to be odd, min 3
SIM_MODE : boolean := false -- enable simulation mode (adding explicit propagation delay)
NUM_INV : natural range 3 to 999 := 3; -- number of inverters, has to be odd, min 3
SIM_MODE : boolean := false -- enable simulation mode (no physical random if enabled!)
);
port (
clk_i : in std_ulogic; -- clock
@ -452,21 +448,21 @@ begin
-- latch with global reset and individual enable --
latch(i) <= '0' when (en_i = '0') else latch(i) when (sreg(i) = '0') else inv_out(i);
-- inverter with simulated propagation delay --
-- inverter with "propagation delay" --
inverter_sim:
if SIM_MODE generate
inv_out(i) <= (not inv_in(i)) after 2 ns; -- for SIMULATION ONLY
inv_out(i) <= not inv_in(i) when rising_edge(clk_i); -- for SIMULATION ONLY
end generate;
-- inverter for actual synthesis --
inverter_phy:
if not SIM_MODE generate
inv_out(i) <= (not inv_in(i));
inv_out(i) <= not inv_in(i);
end generate;
end generate;
-- interconnect --
-- chaining --
inv_in(0) <= latch(NUM_INV-1); -- beginning/end of chain
inv_in(NUM_INV-1 downto 1) <= latch(NUM_INV-2 downto 0); -- inside chain