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minor edits and updates

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stnolting 2020-06-25 20:16:17 +02:00
parent ea0acbe2c7
commit def3cb5ee8
4 changed files with 30 additions and 28 deletions
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1
.gitignore vendored
View file

@ -10,6 +10,7 @@
# no executables
sw/image_gen/image_gen
sw/image_gen/image_gen.exe
# no temp/legacy files/folders
~*

2
sw/common/crt0.S
View file

@ -84,6 +84,8 @@ __crt0_reg_file_init:
addi x15, x14, 0
// the following registers do not exist in rv32e
// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when
// compiling for a rv32e architecture
#ifndef __RISCV_EMBEDDED_CPU__
addi x16, x15, 0
addi x17, x16, 0

21
sw/example/hw_analysis/main.c
View file

@ -150,33 +150,36 @@ int main() {
neorv32_uart_printf("\n-- Peripherals --\n");
tmp = neorv32_cpu_csr_read(CSR_MFEATURES);
neorv32_uart_printf("GPIO: ");
neorv32_uart_printf("GPIO: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));
neorv32_uart_printf("MTIME: ");
neorv32_uart_printf("MTIME: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));
neorv32_uart_printf("UART: ");
neorv32_uart_printf("UART: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));
neorv32_uart_printf("SPI: ");
neorv32_uart_printf("SPI: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));
neorv32_uart_printf("TWI: ");
neorv32_uart_printf("TWI: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));
neorv32_uart_printf("PWM: ");
neorv32_uart_printf("PWM: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));
neorv32_uart_printf("WDT: ");
neorv32_uart_printf("WDT: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));
neorv32_uart_printf("CLIC: ");
neorv32_uart_printf("CLIC: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));
neorv32_uart_printf("TRNG: ");
neorv32_uart_printf("TRNG: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));
neorv32_uart_printf("DEVNULL: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));
return 0;
}

34
sw/example/test_exceptions/main.c
View file

@ -143,11 +143,9 @@ int main() {
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFL;
neorv32_mtime_set_timecmp(mtime_cmp_max);
#if (DETAILED_EXCEPTION_DEBUG==1)
// detailed intro
neorv32_uart_printf("NEORV32 exceptions and interrupts test program: ");
#endif
neorv32_uart_printf("NEORV32 EXC TESTS\n");
// intro
neorv32_uart_printf("\nNEORV32 exceptions and interrupts test program\n\n");
// install exception handler functions
@ -197,7 +195,7 @@ int main() {
// ----------------------------------------------------------
// Unaligned instruction address
// ----------------------------------------------------------
neorv32_uart_printf("I_ALIGN: ");
neorv32_uart_printf("EXC I_ALIGN: ");
cnt_test++;
// call unaligned address
@ -219,7 +217,7 @@ int main() {
// ----------------------------------------------------------
// Instruction access fault
// ----------------------------------------------------------
neorv32_uart_printf("I_ACC: ");
neorv32_uart_printf("EXC I_ACC: ");
cnt_test++;
// call unreachable aligned address
@ -241,7 +239,7 @@ int main() {
// ----------------------------------------------------------
// Illegal instruction
// ----------------------------------------------------------
neorv32_uart_printf("I_ILLEG: ");
neorv32_uart_printf("EXC I_ILLEG: ");
cnt_test++;
// create mini program in RAM
@ -269,7 +267,7 @@ int main() {
// ----------------------------------------------------------
// Breakpoint instruction
// ----------------------------------------------------------
neorv32_uart_printf("BREAK: ");
neorv32_uart_printf("EXC BREAK: ");
cnt_test++;
asm volatile("EBREAK");
@ -290,7 +288,7 @@ int main() {
// ----------------------------------------------------------
// Unaligned load address
// ----------------------------------------------------------
neorv32_uart_printf("L_ALIGN: ");
neorv32_uart_printf("EXC L_ALIGN: ");
cnt_test++;
// load from unaligned address
@ -312,7 +310,7 @@ int main() {
// ----------------------------------------------------------
// Load access fault
// ----------------------------------------------------------
neorv32_uart_printf("L_ACC: ");
neorv32_uart_printf("EXC L_ACC: ");
cnt_test++;
// load from unreachable aligned address
@ -334,7 +332,7 @@ int main() {
// ----------------------------------------------------------
// Unaligned store address
// ----------------------------------------------------------
neorv32_uart_printf("S_ALIGN: ");
neorv32_uart_printf("EXC S_ALIGN: ");
cnt_test++;
// store to unaligned address
@ -356,7 +354,7 @@ int main() {
// ----------------------------------------------------------
// Store access fault
// ----------------------------------------------------------
neorv32_uart_printf("S_ACC: ");
neorv32_uart_printf("EXC S_ACC: ");
cnt_test++;
// store to unreachable aligned address
@ -378,7 +376,7 @@ int main() {
// ----------------------------------------------------------
// Environment call
// ----------------------------------------------------------
neorv32_uart_printf("ENVCALL: ");
neorv32_uart_printf("EXC ENVCALL: ");
cnt_test++;
asm volatile("ECALL");
@ -399,7 +397,7 @@ int main() {
// ----------------------------------------------------------
// Machine software interrupt
// ----------------------------------------------------------
neorv32_uart_printf("MSI: ");
neorv32_uart_printf("IRQ MSI: ");
cnt_test++;
// trigger machine software interrupt
@ -421,7 +419,7 @@ int main() {
// ----------------------------------------------------------
// Machine timer interrupt (MTIME)
// ----------------------------------------------------------
neorv32_uart_printf("MTI: ");
neorv32_uart_printf("IRQ MTI: ");
cnt_test++;
// force MTIME IRQ
@ -449,7 +447,7 @@ int main() {
// ----------------------------------------------------------
// Machine external interrupt (via CLIC)
// ----------------------------------------------------------
neorv32_uart_printf("MEI: ");
neorv32_uart_printf("IRQ MEI: ");
cnt_test++;
// manually trigger CLIC channel (watchdog interrupt)
@ -474,10 +472,8 @@ int main() {
#endif
#if (DETAILED_EXCEPTION_DEBUG==1)
// error report
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail);
#endif
// final result
if (cnt_fail == 0) {