mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-23 13:47:33 -04:00
[sw/lib] cleanup rte
This commit is contained in:
stnolting
parent
162225b5d0
commit
e04396aec2
2 changed files with 129 additions and 220 deletions
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@ -100,9 +100,6 @@ void neorv32_rte_print_hw_version(void);
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void neorv32_rte_print_credits(void);
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void neorv32_rte_print_logo(void);
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void neorv32_rte_print_license(void);
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uint32_t neorv32_rte_get_compiler_isa(void);
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int neorv32_rte_check_isa(int silent);
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/**@}*/
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@ -72,9 +72,6 @@ static void __neorv32_rte_print_hex_word(uint32_t num);
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**************************************************************************/
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void neorv32_rte_setup(void) {
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// raise an exception if we're not in machine-mode
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asm volatile ("csrr x0, mhartid");
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// clear mstatus, set previous privilege level to machine-mode
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neorv32_cpu_csr_write(CSR_MSTATUS, (1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L));
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@ -88,8 +85,8 @@ void neorv32_rte_setup(void) {
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neorv32_cpu_csr_write(CSR_MIP, 0);
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// install debug handler for all trap sources
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uint8_t id;
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for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
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int id;
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for (id = 0; id < ((int)NEORV32_RTE_NUM_TRAPS); id++) {
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neorv32_rte_handler_uninstall(id); // this will configure the debug handler
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}
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}
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@ -111,8 +108,9 @@ int neorv32_rte_handler_install(int id, void (*handler)(void)) {
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asm volatile ("csrr x0, mhartid");
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// id valid?
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if ((id >= (int)RTE_TRAP_I_MISALIGNED) && (id <= (int)RTE_TRAP_FIRQ_15)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler
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uint32_t index = (uint32_t)id;
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if (index < ((uint32_t)NEORV32_RTE_NUM_TRAPS)) {
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__neorv32_rte_vector_lut[index] = (uint32_t)handler; // install handler
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return 0;
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}
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return -1;
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@ -135,8 +133,9 @@ int neorv32_rte_handler_uninstall(int id) {
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asm volatile ("csrr x0, mhartid");
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// id valid?
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if ((id >= (int)RTE_TRAP_I_MISALIGNED) && (id <= (int)RTE_TRAP_FIRQ_15)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_handler); // use dummy handler in case the trap is accidentally triggered
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uint32_t index = (uint32_t)id;
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if (index < ((uint32_t)NEORV32_RTE_NUM_TRAPS)) {
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__neorv32_rte_vector_lut[index] = (uint32_t)(&__neorv32_rte_debug_handler); // use dummy handler in case the trap is accidentally triggered
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return 0;
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}
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return -1;
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@ -202,35 +201,35 @@ static void __attribute__((__naked__,aligned(4))) __neorv32_rte_core(void) {
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uint32_t handler_base;
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switch (neorv32_cpu_csr_read(CSR_MCAUSE)) {
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case TRAP_CODE_I_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
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case TRAP_CODE_I_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
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case TRAP_CODE_I_ILLEGAL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
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case TRAP_CODE_BREAKPOINT: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
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case TRAP_CODE_I_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
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case TRAP_CODE_I_ILLEGAL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
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case TRAP_CODE_BREAKPOINT: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
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case TRAP_CODE_L_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_L_MISALIGNED]; break;
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case TRAP_CODE_L_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break;
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case TRAP_CODE_L_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break;
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case TRAP_CODE_S_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_S_MISALIGNED]; break;
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case TRAP_CODE_S_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
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case TRAP_CODE_UENV_CALL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_UENV_CALL]; break;
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case TRAP_CODE_MENV_CALL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
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case TRAP_CODE_MSI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
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case TRAP_CODE_MTI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break;
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case TRAP_CODE_MEI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break;
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case TRAP_CODE_FIRQ_0: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_0]; break;
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case TRAP_CODE_FIRQ_1: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break;
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case TRAP_CODE_FIRQ_2: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break;
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case TRAP_CODE_FIRQ_3: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break;
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case TRAP_CODE_FIRQ_4: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_4]; break;
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case TRAP_CODE_FIRQ_5: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_5]; break;
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case TRAP_CODE_FIRQ_6: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_6]; break;
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case TRAP_CODE_FIRQ_7: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_7]; break;
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case TRAP_CODE_FIRQ_8: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_8]; break;
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case TRAP_CODE_FIRQ_9: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_9]; break;
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case TRAP_CODE_FIRQ_10: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_10]; break;
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case TRAP_CODE_FIRQ_11: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_11]; break;
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case TRAP_CODE_FIRQ_12: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_12]; break;
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case TRAP_CODE_FIRQ_13: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break;
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case TRAP_CODE_FIRQ_14: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break;
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case TRAP_CODE_FIRQ_15: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break;
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default: handler_base = (uint32_t)(&__neorv32_rte_debug_handler); break;
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case TRAP_CODE_S_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
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case TRAP_CODE_UENV_CALL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_UENV_CALL]; break;
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case TRAP_CODE_MENV_CALL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
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case TRAP_CODE_MSI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
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case TRAP_CODE_MTI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break;
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case TRAP_CODE_MEI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break;
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case TRAP_CODE_FIRQ_0: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_0]; break;
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case TRAP_CODE_FIRQ_1: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break;
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case TRAP_CODE_FIRQ_2: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break;
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case TRAP_CODE_FIRQ_3: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break;
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case TRAP_CODE_FIRQ_4: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_4]; break;
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case TRAP_CODE_FIRQ_5: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_5]; break;
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case TRAP_CODE_FIRQ_6: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_6]; break;
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case TRAP_CODE_FIRQ_7: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_7]; break;
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case TRAP_CODE_FIRQ_8: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_8]; break;
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case TRAP_CODE_FIRQ_9: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_9]; break;
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case TRAP_CODE_FIRQ_10: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_10]; break;
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case TRAP_CODE_FIRQ_11: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_11]; break;
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case TRAP_CODE_FIRQ_12: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_12]; break;
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case TRAP_CODE_FIRQ_13: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break;
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case TRAP_CODE_FIRQ_14: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break;
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case TRAP_CODE_FIRQ_15: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break;
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default: handler_base = (uint32_t)(&__neorv32_rte_debug_handler); break;
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}
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// execute handler
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@ -261,7 +260,7 @@ static void __attribute__((__naked__,aligned(4))) __neorv32_rte_core(void) {
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asm volatile (
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// "lw x0, 0*4(sp) \n"
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"lw x1, 1*4(sp) \n"
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// restore 2x at the very end
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// restore 2x at the very end
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"lw x3, 3*4(sp) \n"
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"lw x4, 4*4(sp) \n"
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"lw x5, 5*4(sp) \n"
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@ -515,7 +514,6 @@ void neorv32_rte_print_hw_config(void) {
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uint32_t tmp;
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int i;
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char c;
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neorv32_uart0_printf("\n\n<< NEORV32 Processor Configuration >>\n\n");
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@ -554,27 +552,25 @@ void neorv32_rte_print_hw_config(void) {
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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for (i=0; i<26; i++) {
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if (tmp & (1 << i)) {
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c = (char)('A' + i);
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neorv32_uart0_putc(c);
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neorv32_uart0_putc((char)('A' + i));
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neorv32_uart0_putc(' ');
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}
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}
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// CPU sub-extensions
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tmp = neorv32_cpu_csr_read(CSR_MXISA);
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if (tmp & (1<<CSR_MXISA_ZICSR)) { neorv32_uart0_printf("Zicsr "); }
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if (tmp & (1<<CSR_MXISA_ZFINX)) { neorv32_uart0_printf("Zfinx "); }
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if (tmp & (1<<CSR_MXISA_ZICNTR)) { neorv32_uart0_printf("Zicntr "); }
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if (tmp & (1<<CSR_MXISA_ZICOND)) { neorv32_uart0_printf("Zicond "); }
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if (tmp & (1<<CSR_MXISA_ZICSR)) { neorv32_uart0_printf("Zicsr "); }
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if (tmp & (1<<CSR_MXISA_ZIFENCEI)) { neorv32_uart0_printf("Zifencei "); }
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if (tmp & (1<<CSR_MXISA_ZFINX)) { neorv32_uart0_printf("Zfinx "); }
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if (tmp & (1<<CSR_MXISA_ZIHPM)) { neorv32_uart0_printf("Zihpm "); }
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if (tmp & (1<<CSR_MXISA_ZMMUL)) { neorv32_uart0_printf("Zmmul "); }
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if (tmp & (1<<CSR_MXISA_ZXCFU)) { neorv32_uart0_printf("Zxcfu "); }
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if (tmp & (1<<CSR_MXISA_SDEXT)) { neorv32_uart0_printf("Sdext "); }
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if (tmp & (1<<CSR_MXISA_SDTRIG)) { neorv32_uart0_printf("Sdtrig "); }
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if (tmp & (1<<CSR_MXISA_PMP)) { neorv32_uart0_printf("Smpmp "); }
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if (tmp & (1<<CSR_MXISA_SMCNTRPMF)) { neorv32_uart0_printf("Smcntrpmf "); }
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if (tmp & (1<<CSR_MXISA_PMP)) { neorv32_uart0_printf("Smpmp "); }
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// CPU tuning options
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neorv32_uart0_printf("\nTuning options: ");
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if (tmp & (1<<CSR_MXISA_FASTMUL)) { neorv32_uart0_printf("fast_mul "); }
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@ -582,7 +578,7 @@ void neorv32_rte_print_hw_config(void) {
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if (tmp & (1<<CSR_MXISA_RFHWRST)) { neorv32_uart0_printf("rf_hw_rst "); }
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// check physical memory protection
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neorv32_uart0_printf("\nPhys. Mem. Prot.: ");
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neorv32_uart0_printf("\nPhys. Memory Prot.: ");
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uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
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if (pmp_num_regions != 0) {
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neorv32_uart0_printf("%u region(s), %u bytes granularity", pmp_num_regions, neorv32_cpu_pmp_get_granularity());
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@ -673,17 +669,27 @@ void neorv32_rte_print_hw_config(void) {
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// reservation set granularity --
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neorv32_uart0_printf("Reservation set: ");
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if (neorv32_cpu_csr_read(CSR_MISA) & (1 << 0)) {
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neorv32_uart0_printf("%u bytes granularity\n", (uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_RVSG]) & 0xFFFFFFFCUL);
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}
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else {
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neorv32_uart0_printf("none\n");
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}
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// external bus interface
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neorv32_uart0_printf("Ext. bus interface: ");
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__neorv32_rte_print_true_false(NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_EXT));
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neorv32_uart0_printf("Ext. bus endianness: ");
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if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_EXT_ENDIAN)) {
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neorv32_uart0_printf("big\n");
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tmp = NEORV32_SYSINFO->SOC;
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if (tmp & (1 << SYSINFO_SOC_MEM_EXT)) {
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neorv32_uart0_printf("Wishbone b4 ");
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if (tmp & (1 << SYSINFO_SOC_MEM_EXT_ENDIAN)) {
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neorv32_uart0_printf("big-endian\n");
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}
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else {
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neorv32_uart0_printf("little-endian\n");
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}
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}
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else {
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neorv32_uart0_printf("little\n");
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neorv32_uart0_printf("none\n");
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}
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// peripherals
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@ -738,19 +744,17 @@ static void __neorv32_rte_print_true_false(int state) {
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**************************************************************************/
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void __neorv32_rte_print_hex_word(uint32_t num) {
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if (neorv32_uart0_available() == 0) {
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return; // cannot output anything if UART0 is not implemented
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}
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int i;
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static const char hex_symbols[16] = "0123456789ABCDEF";
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neorv32_uart0_putc('0');
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neorv32_uart0_putc('x');
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if (neorv32_uart0_available() != 0) { // cannot output anything if UART0 is not implemented
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neorv32_uart0_putc('0');
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neorv32_uart0_putc('x');
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int i;
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for (i=0; i<8; i++) {
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uint32_t index = (num >> (28 - 4*i)) & 0xF;
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neorv32_uart0_putc(hex_symbols[index]);
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for (i=0; i<8; i++) {
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uint32_t index = (num >> (28 - 4*i)) & 0xF;
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neorv32_uart0_putc(hex_symbols[index]);
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}
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}
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}
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@ -766,27 +770,25 @@ void neorv32_rte_print_hw_version(void) {
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uint32_t i;
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char tmp, cnt;
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if (neorv32_uart0_available() == 0) {
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return; // cannot output anything if UART0 is not implemented
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}
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if (neorv32_uart0_available() != 0) { // cannot output anything if UART0 is not implemented
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for (i=0; i<4; i++) {
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for (i=0; i<4; i++) {
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tmp = (char)(neorv32_cpu_csr_read(CSR_MIMPID) >> (24 - 8*i));
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tmp = (char)(neorv32_cpu_csr_read(CSR_MIMPID) >> (24 - 8*i));
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// serial division
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cnt = 0;
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while (tmp >= 16) {
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tmp = tmp - 16;
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cnt++;
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}
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// serial division
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cnt = 0;
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while (tmp >= 16) {
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tmp = tmp - 16;
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cnt++;
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}
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if (cnt) {
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neorv32_uart0_putc('0' + cnt);
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}
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neorv32_uart0_putc('0' + tmp);
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if (i < 3) {
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neorv32_uart0_putc('.');
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if (cnt) {
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neorv32_uart0_putc('0' + cnt);
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}
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neorv32_uart0_putc('0' + tmp);
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if (i < 3) {
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neorv32_uart0_putc('.');
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}
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}
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}
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}
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@ -798,12 +800,10 @@ void neorv32_rte_print_hw_version(void) {
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**************************************************************************/
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void neorv32_rte_print_credits(void) {
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if (neorv32_uart0_available() == 0) {
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return; // cannot output anything if UART0 is not implemented
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if (neorv32_uart0_available() != 0) { // cannot output anything if UART0 is not implemented
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neorv32_uart0_puts("The NEORV32 RISC-V Processor, github.com/stnolting/neorv32\n"
|
||||
"(c) 2023 by Dipl.-Ing. Stephan Nolting, BSD 3-Clause License\n");
|
||||
}
|
||||
|
||||
neorv32_uart0_puts("The NEORV32 RISC-V Processor, github.com/stnolting/neorv32\n"
|
||||
"(c) 2023 by Dipl.-Ing. Stephan Nolting, BSD 3-Clause License\n");
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -829,25 +829,23 @@ void neorv32_rte_print_logo(void) {
|
|||
uint16_t tmp;
|
||||
char c;
|
||||
|
||||
if (neorv32_uart0_available() == 0) {
|
||||
return; // cannot output anything if UART0 is not implemented
|
||||
}
|
||||
|
||||
for (u=0; u<9; u++) {
|
||||
neorv32_uart0_puts("\n");
|
||||
for (v=0; v<7; v++) {
|
||||
tmp = logo_data_c[u][v];
|
||||
for (w=0; w<16; w++){
|
||||
c = ' ';
|
||||
if (((int16_t)tmp) < 0) { // check MSB
|
||||
c = '#';
|
||||
if (neorv32_uart0_available() != 0) { // cannot output anything if UART0 is not implemented
|
||||
for (u=0; u<9; u++) {
|
||||
neorv32_uart0_puts("\n");
|
||||
for (v=0; v<7; v++) {
|
||||
tmp = logo_data_c[u][v];
|
||||
for (w=0; w<16; w++){
|
||||
c = ' ';
|
||||
if (((int16_t)tmp) < 0) { // check MSB
|
||||
c = '#';
|
||||
}
|
||||
neorv32_uart0_putc(c);
|
||||
tmp <<= 1;
|
||||
}
|
||||
neorv32_uart0_putc(c);
|
||||
tmp <<= 1;
|
||||
}
|
||||
}
|
||||
neorv32_uart0_puts("\n");
|
||||
}
|
||||
neorv32_uart0_puts("\n");
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -857,124 +855,38 @@ void neorv32_rte_print_logo(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_rte_print_license(void) {
|
||||
|
||||
if (neorv32_uart0_available() == 0) {
|
||||
return; // cannot output anything if UART0 is not implemented
|
||||
}
|
||||
|
||||
neorv32_uart0_puts(
|
||||
"\n"
|
||||
"BSD 3-Clause License\n"
|
||||
"\n"
|
||||
"Copyright (c) 2023, Stephan Nolting. All rights reserved.\n"
|
||||
"\n"
|
||||
"Redistribution and use in source and binary forms, with or without modification, are\n"
|
||||
"permitted provided that the following conditions are met:\n"
|
||||
"\n"
|
||||
"1. Redistributions of source code must retain the above copyright notice, this list of\n"
|
||||
" conditions and the following disclaimer.\n"
|
||||
"\n"
|
||||
"2. Redistributions in binary form must reproduce the above copyright notice, this list of\n"
|
||||
" conditions and the following disclaimer in the documentation and/or other materials\n"
|
||||
" provided with the distribution.\n"
|
||||
"\n"
|
||||
"3. Neither the name of the copyright holder nor the names of its contributors may be used to\n"
|
||||
" endorse or promote products derived from this software without specific prior written\n"
|
||||
" permission.\n"
|
||||
"\n"
|
||||
"THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS\n"
|
||||
"OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n"
|
||||
"MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n"
|
||||
"COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n"
|
||||
"EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n"
|
||||
"GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n"
|
||||
"AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n"
|
||||
"NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n"
|
||||
"OF THE POSSIBILITY OF SUCH DAMAGE.\n"
|
||||
"\n"
|
||||
"\n"
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* NEORV32 runtime environment (RTE):
|
||||
* Get MISA CSR value according to *compiler/toolchain configuration*.
|
||||
*
|
||||
* @return MISA content according to compiler configuration.
|
||||
**************************************************************************/
|
||||
uint32_t neorv32_rte_get_compiler_isa(void) {
|
||||
|
||||
uint32_t misa_cc = 0;
|
||||
|
||||
#if defined __riscv_atomic || defined __riscv_a
|
||||
misa_cc |= 1 << CSR_MISA_A;
|
||||
#endif
|
||||
|
||||
#ifdef __riscv_b
|
||||
misa_cc |= 1 << CSR_MISA_B;
|
||||
#endif
|
||||
|
||||
#if defined __riscv_compressed || defined __riscv_c
|
||||
misa_cc |= 1 << CSR_MISA_C;
|
||||
#endif
|
||||
|
||||
#if (__riscv_flen == 64) || defined __riscv_d
|
||||
misa_cc |= 1 << CSR_MISA_D;
|
||||
#endif
|
||||
|
||||
#ifdef __riscv_32e
|
||||
misa_cc |= 1 << CSR_MISA_E;
|
||||
#else
|
||||
misa_cc |= 1 << CSR_MISA_I;
|
||||
#endif
|
||||
|
||||
#if (__riscv_flen == 32) || defined __riscv_f
|
||||
misa_cc |= 1 << CSR_MISA_F;
|
||||
#endif
|
||||
|
||||
#if defined __riscv_mul || defined __riscv_m
|
||||
misa_cc |= 1 << CSR_MISA_M;
|
||||
#endif
|
||||
|
||||
#if (__riscv_xlen == 32)
|
||||
misa_cc |= 1 << CSR_MISA_MXL_LO;
|
||||
#elif (__riscv_xlen == 64)
|
||||
misa_cc |= 2 << CSR_MISA_MXL_LO;
|
||||
#else
|
||||
misa_cc |= 3 << CSR_MISA_MXL_LO;
|
||||
#endif
|
||||
|
||||
return misa_cc;
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* NEORV32 runtime environment (RTE):
|
||||
* Check required ISA extensions (via compiler flags) against available ISA extensions (via MISA csr).
|
||||
*
|
||||
* @warning This function can be called from machine-mode only.
|
||||
*
|
||||
* @param[in] silent Show error message (via UART0) if isa_sw > isa_hw when = 0.
|
||||
* @return MISA content according to compiler configuration.
|
||||
**************************************************************************/
|
||||
int neorv32_rte_check_isa(int silent) {
|
||||
|
||||
uint32_t misa_sw = neorv32_rte_get_compiler_isa();
|
||||
uint32_t misa_hw = neorv32_cpu_csr_read(CSR_MISA);
|
||||
|
||||
// mask hardware features that are not used by software
|
||||
uint32_t check = misa_hw & misa_sw;
|
||||
|
||||
if (check == misa_sw) {
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
if ((silent == 0) && (neorv32_uart0_available() != 0)) {
|
||||
neorv32_uart0_printf("\nWARNING! SW_ISA (features required) vs HW_ISA (features available) mismatch!\n"
|
||||
"SW_ISA = 0x%x (compiler flags)\n"
|
||||
"HW_ISA = 0x%x (misa csr)\n\n", misa_sw, misa_hw);
|
||||
}
|
||||
return 1;
|
||||
if (neorv32_uart0_available() != 0) { // cannot output anything if UART0 is not implemented
|
||||
neorv32_uart0_puts(
|
||||
"\n"
|
||||
"BSD 3-Clause License\n"
|
||||
"\n"
|
||||
"Copyright (c) 2023, Stephan Nolting. All rights reserved.\n"
|
||||
"\n"
|
||||
"Redistribution and use in source and binary forms, with or without modification, are\n"
|
||||
"permitted provided that the following conditions are met:\n"
|
||||
"\n"
|
||||
"1. Redistributions of source code must retain the above copyright notice, this list of\n"
|
||||
" conditions and the following disclaimer.\n"
|
||||
"\n"
|
||||
"2. Redistributions in binary form must reproduce the above copyright notice, this list of\n"
|
||||
" conditions and the following disclaimer in the documentation and/or other materials\n"
|
||||
" provided with the distribution.\n"
|
||||
"\n"
|
||||
"3. Neither the name of the copyright holder nor the names of its contributors may be used to\n"
|
||||
" endorse or promote products derived from this software without specific prior written\n"
|
||||
" permission.\n"
|
||||
"\n"
|
||||
"THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS\n"
|
||||
"OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n"
|
||||
"MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n"
|
||||
"COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n"
|
||||
"EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n"
|
||||
"GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n"
|
||||
"AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n"
|
||||
"NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n"
|
||||
"OF THE POSSIBILITY OF SUCH DAMAGE.\n"
|
||||
"\n"
|
||||
"\n"
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue