github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 14:17:51 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[mem] minor comment fix

Browse source
This commit is contained in:
stnolting 2023-10-29 07:25:50 +01:00
parent 271ff66691
commit e234f0f243
4 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

2
rtl/core/mem/neorv32_dmem.default.vhd
View file

@ -49,7 +49,7 @@ architecture neorv32_dmem_rtl of neorv32_dmem is
-- -------------------------------------------------------------------------------------------------------------- --
-- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have --
-- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
-- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive. --
-- [NOTE] Read-during-write behavior is irrelevant as read and write accesses are mutually exclusive. --
-- -------------------------------------------------------------------------------------------------------------- --
-- RAM - not initialized at all --

2
rtl/core/mem/neorv32_dmem.legacy.vhd
View file

@ -50,7 +50,7 @@ architecture neorv32_dmem_rtl of neorv32_dmem is
-- -------------------------------------------------------------------------------------------------------------- --
-- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have --
-- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
-- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive. --
-- [NOTE] Read-during-write behavior is irrelevant as read and write accesses are mutually exclusive. --
-- -------------------------------------------------------------------------------------------------------------- --
-- RAM - not initialized at all --

2
rtl/core/mem/neorv32_imem.default.vhd
View file

@ -66,7 +66,7 @@ architecture neorv32_imem_rtl of neorv32_imem is
-- -------------------------------------------------------------------------------------------------------------- --
-- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have --
-- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
-- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive. --
-- [NOTE] Read-during-write behavior is irrelevant as read and write accesses are mutually exclusive. --
-- -------------------------------------------------------------------------------------------------------------- --
-- RAM - not initialized at all --

2
rtl/core/mem/neorv32_imem.legacy.vhd
View file

@ -67,7 +67,7 @@ architecture neorv32_imem_rtl of neorv32_imem is
-- -------------------------------------------------------------------------------------------------------------- --
-- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have --
-- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
-- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive. --
-- [NOTE] Read-during-write behavior is irrelevant as read and write accesses are mutually exclusive. --
-- -------------------------------------------------------------------------------------------------------------- --
-- RAM - not initialized at all --