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[rtl/core/twi] delay sda low (#1237)
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stnolting 2025-04-18 22:41:51 +02:00 • committed by GitHub
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3 changed files with 3 additions and 2 deletions
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1
CHANGELOG.md
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 18.04.2025 | 1.11.2.9 | adjust TWI timing to allow for repeated-start at higher TWI clock speeds | [#1237](https://github.com/stnolting/neorv32/pull/1237) |
| 18.04.2025 | 1.11.2.8 | :bug: fix bug in PMP logic: multiple signal assignments when NAPOT-mode is disabled | [#1236](https://github.com/stnolting/neorv32/pull/1236) |
| 12.04.2025 | 1.11.2.7 | :sparkles: add PWM polarity configuration | [#1230](https://github.com/stnolting/neorv32/pull/1230) |
| 07.04.2025 | 1.11.2.6 | :bug: fix SDI input synchronization | [#1227](https://github.com/stnolting/neorv32/pull/1227) |

2
rtl/core/neorv32_package.vhd
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@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110208"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110209"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

2
rtl/core/neorv32_twi.vhd
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@ -333,7 +333,7 @@ begin
-- ------------------------------------------------------------
if (clk_gen.phase(0) = '1') then
io_con.sda_out <= '1';
elsif (clk_gen.phase(1) = '1') then
elsif (clk_gen.phase(2) = '1') then
io_con.sda_out <= '0';
end if;
--