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[docs] minor TRNG updates

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stnolting 2022-05-06 19:50:19 +02:00
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22
docs/datasheet/soc_trng.adoc
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@ -21,21 +21,24 @@ Instead of using a pseudo RNG like a LFSR, the TRNG uses a simple, straight-forw
oscillator concept as physical entropy source. Hence, voltage, thermal and also semiconductor manufacturing
fluctuations are used to provide a true physical entropy source.
The TRNG is based on the _neoTRNG_, which is a "spin-off project" of the
NEORV32 processor. The TRNG uses the default neoTRNG configuration, which showed very good results in the
`dieharder` battery of random number tests. More detailed information about the neoTRNG, it's architecture and a
detailed evaluation of the random number quality can be found it it's repository: https://github.com/stnolting/neoTRNG
.Platform Independent Architecture
[NOTE]
The TRNG features a platform independent architecture without FPGA-specific primitives, macros or
attributes so it can be synthesized for _any_ FPGA.
The TRNG is based on the **neoTRNG V2**, which is a "spin-off project" of the
NEORV32 processor. More detailed information about the neoTRNG, it's architecture and a
detailed evaluation of the random number quality can be found it it's repository: https://github.com/stnolting/neoTRNG
.Inferring Latches
[NOTE]
The synthesis tool might emit a warning like _"inferring latches for ... neorv32_trng ..."_. This is no problem
as this is what we actually want (the TRNG is based on latches).
.Simulation
[IMPORTANT]
When simulating the processor the TRNG is automatically set to "simulation mode". In this mode, the physical entropy
sources (= the ring oscillators) are replaced by a simple **pseudo RNG (LFSR)** providing very weak random data only.
The _TRNG_CTRL_SIM_MODE_ flag of the control register is set if simulation mode is active.
**Using the TRNG**
@ -48,7 +51,7 @@ entropy source. The _TRNG_CTRL_VALID_ bit is automatically cleared when reading
.TRNG Reset
[NOTE]
The TRNG core does not provide a dedicated reset. In order to ensure correct operations, the TRNG should be
disabled (=reset) by clearing the _TRNG_CTRL_EN_ and waiting some milliseconds before re-enabling it.
disabled (=reset) by clearing the _TRNG_CTRL_EN_ and waiting some 1000s clock cycles before re-enabling it.
.TRNG register map (`struct NEORV32_TRNG`)
@ -56,7 +59,8 @@ disabled (=reset) by clearing the _TRNG_CTRL_EN_ and waiting some milliseconds b
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.3+<| `0xffffffb8` .3+<| `NEORV32_TRNG.CTRL` <|`7:0` _TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_MSB_ ^| r/- <| 8-bit random data
.4+<| `0xffffffb8` .4+<| `NEORV32_TRNG.CTRL` <|`7:0` _TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_MSB_ ^| r/- <| 8-bit random data
<|`29` _TRNG_CTRL_SIM_MODE_ ^| r/- <| simulation mode (PRNG!)
<|`30` _TRNG_CTRL_EN_ ^| r/w <| TRNG enable
<|`31` _TRNG_CTRL_VALID_ ^| r/- <| random data is valid when set
|=======================

8
docs/userguide/simulating_the_processor.adoc
View file

@ -22,8 +22,12 @@ Note that this flag is not guaranteed to be set correctly (depending on the HDL
A plain-VHDL (no third-party libraries) testbench (`sim/simple/neorv32_tb.simple.vhd`) can be used for simulating and
testing the processor.
This testbench features a 100MHz clock and enables all optional peripheral and CPU extensions except for the `E`
extension and the TRNG IO module (that CANNOT be simulated due to its combinatorial (looped) architecture).
This testbench features a 100MHz clock and enables all optional peripheral and CPU extensions except for the `E`.
.True Random Number Generator
[NOTE]
The NEORV32 TRNG will be set to "simulation mode" when enabled for simulation (replacing the ring-oscillators
by pseudo-random LFSRs). See the neoTRNG documentation for more information.
The simulation setup is configured via the "User Configuration" section located right at the beginning of
the testbench's architecture. Each configuration constant provides comments to explain the functionality.