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[docs] update FPU fused/MAC section

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stnolting 2024-05-18 17:35:09 +02:00
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10
docs/datasheet/cpu.adoc
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@ -680,10 +680,14 @@ register file-related load/store or move instructions. The `Zfinx` extension'S f
via dedicated <<_floating_point_csrs>>.
This ISA extension is implemented as multi-cycle ALU co-process (`rtl/core/neorv32_cpu_cp_fpu.vhd`).
.Fused Multiply-Add and Division Instructions
.Fused / Multiply-Add Instructions
[WARNING]
Fused multiply-add instructions `f[n]m[add/sub].s` are not supported!
Division `fdiv.s` and square root `fsqrt.s` instructions are not supported yet!
Fused multiply-add instructions `f[n]m[add/sub].s` are not supported. A special GCC switch is used to prevent the
compiler from emitting contracted/fused floating-point operations (see <<_default_compiler_flags>>).
.Division and Squarer Root Instructions
[WARNING]
Division `fdiv.s` and square root `fsqrt.s` instructions are not supported yet.
.Subnormal Number
[WARNING]

1
docs/datasheet/software.adoc
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@ -286,6 +286,7 @@ The makefile's `CC_OPTS` is exported as **define** to be available within a C pr
| `-g` | Include debugging information/symbols in ELF.
| `-mstrict-align` | Unaligned memory accesses cannot be resolved by the hardware and require emulation.
| `-mbranch-cost=10` | Branching costs a lot of cycles.
| `-ffp-contract=off` | Do not allow contraction of floatind-point operations (no fused operations as they are not supported).
|=======================
:sectnums: