github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-23 13:47:33 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

[sw/lib] add Zicond MXISA bit

Browse source
This commit is contained in:
stnolting 2023-12-01 21:38:45 +01:00
parent 446a1b37d3
commit e5bcc74182
3 changed files with 3 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
docs/datasheet/cpu_csr.adoc
View file

@ -1032,7 +1032,7 @@ discover ISA sub-extensions and CPU configuration options
| 3 | `CSR_MXISA_ZXCFU` | r/- | <<_zxcfu_isa_extension>> available
| 4 | `CSR_MXISA_SMCNTRPMF` | r/- | <<_smcntrpmf_isa_extension>> available
| 5 | `CSR_MXISA_ZFINX` | r/- | <<_zfinx_isa_extension>> available
| 6 | - | r/- | hardwired to zero
| 6 | `CSR_MXISA_ZICOND` | r/- | <<_zicond_isa_extension>> available
| 7 | `CSR_MXISA_ZICNTR` | r/- | <<_zicntr_isa_extension>> available
| 8 | `CSR_MXISA_PMP` | r/- | <<_pmp_isa_extension>> available
| 9 | `CSR_MXISA_ZIHPM` | r/- | <<_zihpm_isa_extension>> available

2
sw/lib/include/neorv32_cpu_csr.h
View file

@ -377,7 +377,7 @@ enum NEORV32_CSR_XISA_enum {
CSR_MXISA_ZXCFU = 3, /**< CPU mxisa CSR (3): custom RISC-V instructions (r/-)*/
CSR_MXISA_SMCNTRPMF = 4, /**< CPU mxisa CSR (4): counter privilege mode filtering (r/-)*/
CSR_MXISA_ZFINX = 5, /**< CPU mxisa CSR (5): FPU using x registers (r/-)*/
CSR_MXISA_ZICOND = 6, /**< CPU mxisa CSR (6): integer conditional operations (r/-)*/
CSR_MXISA_ZICNTR = 7, /**< CPU mxisa CSR (7): standard instruction, cycle and time counter CSRs (r/-)*/
CSR_MXISA_PMP = 8, /**< CPU mxisa CSR (8): physical memory protection ("Smpmp") (r/-)*/
CSR_MXISA_ZIHPM = 9, /**< CPU mxisa CSR (9): hardware performance monitors (r/-)*/

1
sw/lib/source/neorv32_rte.c
View file

@ -564,6 +564,7 @@ void neorv32_rte_print_hw_config(void) {
tmp = neorv32_cpu_csr_read(CSR_MXISA);
if (tmp & (1<<CSR_MXISA_ZICSR)) { neorv32_uart0_printf("Zicsr "); }
if (tmp & (1<<CSR_MXISA_ZICNTR)) { neorv32_uart0_printf("Zicntr "); }
if (tmp & (1<<CSR_MXISA_ZICOND)) { neorv32_uart0_printf("Zicond "); }
if (tmp & (1<<CSR_MXISA_ZIFENCEI)) { neorv32_uart0_printf("Zifencei "); }
if (tmp & (1<<CSR_MXISA_ZFINX)) { neorv32_uart0_printf("Zfinx "); }
if (tmp & (1<<CSR_MXISA_ZIHPM)) { neorv32_uart0_printf("Zihpm "); }