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docs: split User Guide
This commit is contained in:
umarcor
parent
9f838c1861
commit
e78e43d15b
39 changed files with 152 additions and 67 deletions
24
.github/workflows/Documentation.yml
vendored
24
.github/workflows/Documentation.yml
vendored
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@ -46,22 +46,14 @@ jobs:
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with:
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fetch-depth: 0
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- name: '📚 Build Datasheet (PDF and HTML)'
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- name: '📚 Build Datasheet and User Guide (PDF and HTML)'
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run: make container
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- name: '📤 Upload Artifact: PDF'
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uses: actions/upload-artifact@v2
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with:
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name: NEORV32-PDF
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path: docs/NEORV32.pdf
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- name: '📤 Upload Artifact: HTML'
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uses: actions/upload-artifact@v2
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with:
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name: NEORV32-HTML
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path: |
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docs/index.html
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docs/figures
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name: NEORV32
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path: docs/public
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deploy:
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@ -82,11 +74,13 @@ jobs:
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- name: '🛠️ Organise public subdir and create a tarball'
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run: |
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mv NEORV32-HTML public
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mv NEORV32 public
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mv public/pdf ./
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mv NEORV32-Doxygen public/sw
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tar zvcf NEORV32-SITE-nightly.tar.gz -C public .
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mv NEORV32-PDF/NEORV32.pdf public
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cp public/NEORV32.pdf NEORV32-nightly.pdf
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cd pdf
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mv NEORV32.pdf NEORV32-nightly.pdf
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mv NEORV32_UserGuide.pdf NEORV32_UserGuide-nightly.pdf
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# Tagged: create a pre-release or a release (semver)
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# Untagged: update the assets of pre-release 'nightly'
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@ -97,7 +91,7 @@ jobs:
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tag: 'nightly'
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files: |
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NEORV32-SITE-nightly.tar.gz
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NEORV32-nightly.pdf
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pdf/NEORV32*nightly.pdf
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- name: '🚀 Deploy to GitHub-Pages'
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run: |
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|
|
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7
.gitignore
vendored
7
.gitignore
vendored
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@ -18,10 +18,9 @@ sw/image_gen/image_gen.exe
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~*
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# no generated documentation stuff
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docs/doxygen_build
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docs/NEORV32.pdf
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/docs/.asciidoctor
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/docs/index.html
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/docs/doxygen_build/
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/docs/.asciidoctor/
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/docs/public/
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# no compiled ghdl stuff
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*.cf
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|
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43
Makefile
43
Makefile
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@ -1,14 +1,18 @@
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.DEFAULT_GOAL := help
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all: pdf html ug-pdf ug-html
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mkdir -p docs/public/img/
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cp -vr docs/figures/* docs/public/img/
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# Generate PDF datasheet
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pdf:
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cd docs; \
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[ -f revnumber.txt ] && REVNUMBER='-a revnumber='"$$(cat revnumber.txt)" || unset REVNUMBER; \
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asciidoctor-pdf $$REVNUMBER \
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-a pdf-theme=src_adoc/neorv32-theme.yml \
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-a pdf-theme=neorv32-theme.yml \
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-r asciidoctor-diagram \
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src_adoc/neorv32.adoc \
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--out-file NEORV32.pdf
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datasheet/main.adoc \
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--out-file public/pdf/NEORV32.pdf
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# Generate HTML datasheet
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html:
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@ -16,8 +20,27 @@ html:
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[ -f revnumber.txt ] && REVNUMBER='-a revnumber='"$$(cat revnumber.txt)" || unset REVNUMBER; \
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asciidoctor $$REVNUMBER \
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-r asciidoctor-diagram \
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src_adoc/index.adoc \
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--out-file index.html
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datasheet/index.adoc \
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--out-file public/index.html
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# Generate PDF user guide
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ug-pdf:
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cd docs; \
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[ -f revnumber.txt ] && REVNUMBER='-a revnumber='"$$(cat revnumber.txt)" || unset REVNUMBER; \
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asciidoctor-pdf $$REVNUMBER \
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-a pdf-theme=neorv32-theme.yml \
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-r asciidoctor-diagram \
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userguide/main.adoc \
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--out-file public/pdf/NEORV32_UserGuide.pdf
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# Generate HTML user guide
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ug-html:
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cd docs; \
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[ -f revnumber.txt ] && REVNUMBER='-a revnumber='"$$(cat revnumber.txt)" || unset REVNUMBER; \
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asciidoctor $$REVNUMBER \
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-r asciidoctor-diagram \
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userguide/index.adoc \
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--out-file public/ug/index.html
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# Generate revnumber.txt for overriding the revnumber attribute in 'pdf' and/or 'html'
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revnumber:
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@ -27,11 +50,13 @@ revnumber:
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# Build 'pdf' and 'html' in an 'asciidoctor-wavedrom' container
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container: revnumber
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docker run --rm -v /$(PWD)://documents/ btdi/asciidoctor make pdf html
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docker run --rm -v /$(PWD)://documents/ btdi/asciidoctor make all
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# Help
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help:
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@echo "Targets:"
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@echo " help - show this text"
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@echo " html - build project documentation as HTML page (docs/index.html)"
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@echo " pdf - build project documentation as pdf file (docs/NEORV32.pdf)"
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@echo " help - show this text"
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@echo " pdf - build datasheet as pdf file (docs/public/pdf/NEORV32.pdf)"
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@echo " html - build datasheet as HTML page (docs/public/index.html)"
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@echo " ug-pdf - build user guide as pdf file (docs/public/pdf/NEORV32_UserGuide.pdf)"
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@echo " ug-html - build user guide as HTML page (docs/public/ug/index.html)"
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|
|
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@ -11,7 +11,9 @@
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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||||
[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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||||
[](https://stnolting.github.io/neorv32)
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||||
[](https://stnolting.github.io/neorv32)
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||||
[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/sw/files.html)
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* [Overview](#Overview)
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|
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@ -11,6 +11,4 @@ include::software.adoc[]
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include::on_chip_debugger.adoc[]
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include::getting_started.adoc[]
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include::legal.adoc[]
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include::../legal.adoc[]
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@ -1,4 +1,5 @@
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= The NEORV32 RISC-V Processor
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= The NEORV32 RISC-V Processor: Datasheet
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:title: [Datasheet] The NEORV32 RISC-V Processor
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:author: Dipl.-Ing. Stephan Nolting
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:email: stnolting@gmail.com
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:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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|
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@ -6,14 +7,14 @@
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:doctype: book
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:sectnums:
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:icons: font
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:imagesdir: figures
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:imagesdir: img
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:stem:
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:reproducible:
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||||
:listing-caption: Listing
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:toc: left
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:toclevels: 4
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:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
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:favicon: figures/icon.png
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:favicon: img/icon.png
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image::neorv32_logo_transparent.png[align=center]
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@ -23,6 +24,8 @@ image::riscv_logo.png[width=350,align=center]
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https://github.com/stnolting/neorv32[image:https://img.shields.io/badge/GitHub-stnolting%2Fneorv32-ffbd00?style=flat-square&logo=github&[title='homepage']]
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||||
https://github.com/stnolting/neorv32/blob/master/LICENSE[image:https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square[title='license']]
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||||
https://github.com/stnolting/neorv32/releases/tag/nightly[image:https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor[title='datasheet (pdf)']]
|
||||
https://github.com/stnolting/neorv32/releases/tag/nightly[image:https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor[title='userguide (pdf)']]
|
||||
https://stnolting.github.io/neorv32/ug[image:https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square[title='userguide (html)']]
|
||||
https://stnolting.github.io/neorv32/sw/files.html[image:https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&style=flat-square&logo=Doxygen[title='doxygen']]
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@ -1,4 +1,4 @@
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= The NEORV32 RISC-V Processor
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= The NEORV32 RISC-V Processor: Datasheet
|
||||
:author: Dipl.-Ing. Stephan Nolting
|
||||
:email: stnolting@gmail.com
|
||||
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
|
||||
|
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@ -6,7 +6,7 @@
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|||
:doctype: book
|
||||
:sectnums:
|
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:icons: image
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:iconsdir: icons
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:iconsdir: ../icons
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:imagesdir: ../figures
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:stem:
|
||||
:reproducible:
|
||||
|
|
@ -14,8 +14,6 @@
|
|||
:toc: macro
|
||||
:toclevels: 4
|
||||
:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
|
||||
// Uncomment next line to add a title page (or set doctype to book)
|
||||
//:title-page:
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||||
// Uncomment next line to set page size (default is A4)
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||||
//:pdf-page-size: Letter
|
||||
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||||
|
Before Width: | Height: | Size: 22 KiB After Width: | Height: | Size: 22 KiB |
|
Before Width: | Height: | Size: 19 KiB After Width: | Height: | Size: 19 KiB |
|
Before Width: | Height: | Size: 15 KiB After Width: | Height: | Size: 15 KiB |
|
Before Width: | Height: | Size: 19 KiB After Width: | Height: | Size: 19 KiB |
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@ -1,11 +1,10 @@
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|||
:sectnums:
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== Let's Get It Started!
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Let's Get It Started!
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To make your NEORV32 project run, follow the guides from the upcoming sections. Follow these guides
|
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step by step and in the presented order.
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:sectnums:
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=== Toolchain Setup
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== Toolchain Setup
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||||
There are two possibilities to get the actual RISC-V GCC toolchain:
|
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@ -24,7 +23,7 @@ emulation) on an architecture without these extensions!
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|||
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||||
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:sectnums:
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||||
==== Building the Toolchain from Scratch
|
||||
=== Building the Toolchain from Scratch
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||||
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To build the toolchain by yourself you can follow the guide from the official https://github.com/riscv/riscvgnu-toolchain GitHub page.
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|
@ -64,7 +63,7 @@ After a while you will get `riscv32-unknown-elf-gcc` and all of its friends in y
|
|||
|
||||
|
||||
:sectnums:
|
||||
==== Downloading and Installing a Prebuilt Toolchain
|
||||
=== Downloading and Installing a Prebuilt Toolchain
|
||||
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Alternatively, you can download a prebuilt toolchain.
|
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@ -89,7 +88,7 @@ CPU extensions that are not supported by the NEORV32 (like `D`).
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:sectnums:
|
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==== Installation
|
||||
=== Installation
|
||||
|
||||
Now you have the binaries. The last step is to add them to your `PATH` environment variable (if you have not
|
||||
already done so). Make sure to add the binaries folder (`bin`) of your toolchain.
|
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|
@ -103,7 +102,7 @@ You should add this command to your `.bashrc` (if you are using bash) to automat
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|||
toolchain at every console start.
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|
||||
:sectnums:
|
||||
==== Testing the Installation
|
||||
=== Testing the Installation
|
||||
|
||||
To make sure everything works fine, navigate to an example project in the NEORV32 example folder and
|
||||
execute the following command:
|
||||
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|
@ -120,7 +119,7 @@ This will test all the tools required for the NEORV32. Everything is working fin
|
|||
<<<
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// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== General Hardware Setup
|
||||
== General Hardware Setup
|
||||
|
||||
The following steps are required to generate a bitstream for your FPGA board. If you want to run the
|
||||
NEORV32 processor in simulation only, the following steps might also apply.
|
||||
|
|
@ -234,7 +233,7 @@ flashing now and you should receive the bootloader start prompt in your UART con
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== General Software Framework Setup
|
||||
== General Software Framework Setup
|
||||
|
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While your synthesis tool is crunching the NEORV32 HDL files, it is time to configure the project's software
|
||||
framework for your processor hardware setup.
|
||||
|
|
@ -287,7 +286,7 @@ _MEM_INT_DMEM_SIZE_ generic).
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Application Program Compilation
|
||||
== Application Program Compilation
|
||||
|
||||
[start=1]
|
||||
. Open a terminal console and navigate to one of the project's example programs. For instance navigate to the
|
||||
|
|
@ -328,7 +327,7 @@ shows the actual assembly code of the complete application.
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Uploading and Starting of a Binary Executable Image via UART
|
||||
== Uploading and Starting of a Binary Executable Image via UART
|
||||
|
||||
You have just created the executable. Now it is time to upload it to the processor. There are basically two
|
||||
options to do so.
|
||||
|
|
@ -455,7 +454,7 @@ Blinking LED demo program
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Setup of a New Application Program Project
|
||||
== Setup of a New Application Program Project
|
||||
|
||||
Done with all the introduction tutorials and those example programs? Then it is time to start your own
|
||||
application project!
|
||||
|
|
@ -510,7 +509,7 @@ All the assignments made to the makefile variable can also be done "inline" when
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Enabling RISC-V CPU Extensions
|
||||
== Enabling RISC-V CPU Extensions
|
||||
|
||||
Whenever you enable/disable a RISC-V CPU extensions via the according _CPU_EXTENSION_RISCV_x_ generic, you need to
|
||||
adapt the toolchain configuration so the compiler can actually generate according code for it.
|
||||
|
|
@ -548,7 +547,7 @@ The RISC-V ISA string (for _MARCH_) follows a certain canonical structure:
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Building a Non-Volatile Application without External Boot Memory
|
||||
== Building a Non-Volatile Application without External Boot Memory
|
||||
|
||||
The primary purpose of the bootloader is to allow an easy and fast update of the current application. In particular, this is very handy
|
||||
during the development stage of a project as you can upload modified programs at any time via the UART.
|
||||
|
|
@ -616,7 +615,7 @@ in the processor's IMEM and is directly executed after reset.
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Customizing the Internal Bootloader
|
||||
== Customizing the Internal Bootloader
|
||||
|
||||
The bootloader provides several configuration options to customize it for your specific applications. The
|
||||
most important user-defined configuration options are available as C `#defines` right at the beginning of the
|
||||
|
|
@ -714,10 +713,10 @@ minimal `rv32i` ISA only (`rv32e` would be even better).
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Programming an External SPI Flash via the Bootloader
|
||||
== Programming an External SPI Flash via the Bootloader
|
||||
|
||||
As described in section <<_external_spi_flash_for_booting>> the bootloader provides an option to store an application image to an external SPI flash
|
||||
and to read this image back for booting. These steps show how to store a
|
||||
and to read this image back for booting. These steps show how to store a
|
||||
|
||||
[start=1]
|
||||
. At first, reset the NEORV32 processor and wait until the bootloader start screen appears in your terminal program.
|
||||
|
|
@ -768,7 +767,7 @@ any user interaction.
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Simulating the Processor
|
||||
== Simulating the Processor
|
||||
|
||||
**Testbench**
|
||||
|
||||
|
|
@ -875,7 +874,7 @@ neorv32/sim$ sh ghdl_sim.sh --stop-time=4ms
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Building the Software Framework Documentation
|
||||
== Building the Software Framework Documentation
|
||||
|
||||
All core library software sources (libraries `sw/lib`, example programs `sw/example`, ...) are highly documented using _doxygen_.
|
||||
To build the documentation by yourself navigate to the project's `doc` folder and run _doxygen_:
|
||||
|
|
@ -896,7 +895,7 @@ The documentation is automatically built and deployed to GitHub pages by a CI wo
|
|||
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Building the Project Documentation
|
||||
== Building the Project Documentation
|
||||
|
||||
This data sheet is written using `asciidoc`. The source files are locates in `docs/src_adoc`.
|
||||
a makefiles in project's root directory is provided to either build a single pdf file
|
||||
|
|
@ -925,7 +924,7 @@ a _docker container_ via `make container`.
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== FreeRTOS Support
|
||||
== FreeRTOS Support
|
||||
|
||||
A NEORV32-specific port and a simple demo for FreeRTOS (https://github.com/FreeRTOS/FreeRTOS) are
|
||||
available in the `sw/example/demo_freeRTOS` folder.
|
||||
|
|
@ -936,7 +935,7 @@ See the according documentation (`sw/example/demo_freeRTOS/README.md`) for more
|
|||
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== RISC-V Architecture Test Framework
|
||||
== RISC-V Architecture Test Framework
|
||||
|
||||
The NEORV32 Processor passes the according tests provided by the official RISC-V Architecture Test Suite
|
||||
(V2.0+), which is available online at GitHub: https://github.com/riscv/riscv-arch-test
|
||||
|
|
@ -951,7 +950,7 @@ file for more information on how to run the tests and how testing is conducted i
|
|||
<<<
|
||||
// ####################################################################################################################
|
||||
:sectnums:
|
||||
=== Debugging using the On-Chip Debugger
|
||||
== Debugging using the On-Chip Debugger
|
||||
|
||||
The NEORV32 <<_on_chip_debugger_ocd>> allows _online_ in-system debugging via an external JTAG access port from a
|
||||
host machine. The general flow is independent of the host machine's operating system. However, this tutorial uses
|
||||
|
|
@ -964,7 +963,7 @@ processor setup _with_ internal instruction memory (IMEM) make sure it is implem
|
|||
|
||||
|
||||
:sectnums:
|
||||
==== Hardware Requirements
|
||||
=== Hardware Requirements
|
||||
|
||||
Make sure the on-chip debugger of your NEORV32 setups is implemented (_ON_CHIP_DEBUGGER_EN_ generic = true).
|
||||
Connect a JTAG adapter to the NEORV32 `jtag_*` interface signals. If you do not have a full-scale JTAG adapter, you can
|
||||
|
|
@ -988,7 +987,7 @@ If TRST is not used make sure to pull the signal _high_.
|
|||
|
||||
|
||||
:sectnums:
|
||||
==== OpenOCD
|
||||
=== OpenOCD
|
||||
|
||||
The NEORV32 on-chip debugger can be accessed using the https://github.com/riscv/riscv-openocd[RISC-V port of OpenOCD].
|
||||
Prebuilt binaries can be obtained - for example - from https://www.sifive.com/software[SiFive]. A pre-configured
|
||||
|
|
@ -1030,7 +1029,7 @@ the `misa` CSRs). Now you can use `gdb` to connect via port 3333.
|
|||
|
||||
|
||||
:sectnums:
|
||||
==== Debugging with GDB
|
||||
=== Debugging with GDB
|
||||
|
||||
This guide uses the simple "blink example" from `sw/example/blink_led` as simplified test application to
|
||||
show the basics of in-system debugging.
|
||||
|
|
@ -1112,7 +1111,7 @@ and halting the CPU right before executing the `blink_led` application.
|
|||
|
||||
|
||||
:sectnums:
|
||||
===== Breakpoint Example
|
||||
==== Breakpoint Example
|
||||
|
||||
The following steps are just a small showcase that illustrate a simple debugging scheme.
|
||||
|
||||
|
|
@ -1133,7 +1132,7 @@ of the counter.
|
|||
690: 00008067 ret
|
||||
--------------------------
|
||||
|
||||
The very last instruction of the `neorv32_cpu_delay_ms` function is `ret` (= return)
|
||||
The very last instruction of the `neorv32_cpu_delay_ms` function is `ret` (= return)
|
||||
at hexadecimal `690` in this example. Add this address as _breakpoint_ to GDB.
|
||||
|
||||
[NOTE]
|
||||
|
|
@ -1166,3 +1165,4 @@ Breakpoint 1, 0x00000690 in neorv32_cpu_delay_ms ()
|
|||
Continuing.
|
||||
--------------------------
|
||||
|
||||
include::../legal.adoc[]
|
||||
32
docs/userguide/index.adoc
Normal file
32
docs/userguide/index.adoc
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
= The NEORV32 RISC-V Processor: User Guide
|
||||
:title: [User Guide] The NEORV32 RISC-V Processor
|
||||
:author: Dipl.-Ing. Stephan Nolting
|
||||
:email: stnolting@gmail.com
|
||||
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
|
||||
:revnumber: v1.5.6.0
|
||||
:doctype: book
|
||||
:sectnums:
|
||||
:icons: font
|
||||
:imagesdir: ../img
|
||||
:stem:
|
||||
:reproducible:
|
||||
:listing-caption: Listing
|
||||
:toc: left
|
||||
:toclevels: 4
|
||||
:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
|
||||
:favicon: ../img/icon.png
|
||||
|
||||
image::neorv32_logo_transparent.png[align=center]
|
||||
|
||||
image::riscv_logo.png[width=350,align=center]
|
||||
|
||||
[.text-center]
|
||||
https://github.com/stnolting/neorv32[image:https://img.shields.io/badge/GitHub-stnolting%2Fneorv32-ffbd00?style=flat-square&logo=github&[title='homepage']]
|
||||
https://github.com/stnolting/neorv32/blob/master/LICENSE[image:https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square[title='license']]
|
||||
https://github.com/stnolting/neorv32/releases/tag/nightly[image:https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor[title='datasheet (pdf)']]
|
||||
https://stnolting.github.io/neorv32[image:https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square[title='datasheet (html)']]
|
||||
https://github.com/stnolting/neorv32/releases/tag/nightly[image:https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor[title='userguide (pdf)']]
|
||||
https://stnolting.github.io/neorv32/sw/files.html[image:https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&style=flat-square&logo=Doxygen[title='doxygen']]
|
||||
|
||||
|
||||
include::content.adoc[]
|
||||
34
docs/userguide/main.adoc
Normal file
34
docs/userguide/main.adoc
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
= The NEORV32 RISC-V Processor: User Guide
|
||||
:author: Dipl.-Ing. Stephan Nolting
|
||||
:email: stnolting@gmail.com
|
||||
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
|
||||
:revnumber: v1.5.6.0
|
||||
:doctype: book
|
||||
:sectnums:
|
||||
:icons: image
|
||||
:iconsdir: ../icons
|
||||
:imagesdir: ../figures
|
||||
:stem:
|
||||
:reproducible:
|
||||
:listing-caption: Listing
|
||||
:toc: macro
|
||||
:toclevels: 4
|
||||
:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
|
||||
// Uncomment next line to set page size (default is A4)
|
||||
//:pdf-page-size: Letter
|
||||
|
||||
|
||||
<<<
|
||||
// ####################################################################################################################
|
||||
.**Documentation**
|
||||
[TIP]
|
||||
The online documentation of the project (a.k.a. the **data sheet**) is available on GitHub-pages: https://stnolting.github.io/neorv32/ +
|
||||
+
|
||||
The online documentation of the **software framework** is also available on GitHub-pages: https://stnolting.github.io/neorv32/sw/files.html
|
||||
|
||||
|
||||
<<<
|
||||
// ####################################################################################################################
|
||||
toc::[]
|
||||
|
||||
include::content.adoc[]
|
||||
Loading…
Add table
Add a link
Reference in a new issue