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[docs] update section WDT

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docs/datasheet/soc_wdt.adoc
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@ -10,90 +10,69 @@
| | neorv32_wdt.h |
| Top entity port: | none |
| Configuration generics: | _IO_WDT_EN_ | implement watchdog when _true_
| CPU interrupts: | fast IRQ channel 0 | watchdog timer overflow (see <<_processor_interrupts>>)
| CPU interrupts: | fast IRQ channel 0 | watchdog timeout (see <<_processor_interrupts>>)
|=======================
**Theory of Operation**
The watchdog (WDT) provides a last resort for safety-critical applications. The WDT provides an internal 20-bit
wide counter that needs to be reset every now and then by the user program. If the counter overflows, either
a system reset or an interrupt is generated depending on the configured operation mode.
The watchdog (WDT) provides a last resort for safety-critical applications. The WDT provides a "bark and bite"
concept. The timeout counter first triggers an optional CPU interrupt ("bark") when reaching half of the programmed
interval to inform the application of the imminent timeout. When the full timeout value is reached
a system-wide hardware reset is generated ("bite"). The internal counter has to be reset explicitly by the application
program every now and then to prevent a timeout.
**Access Password**
**Configuration**
Whenever the watchdog control register `NEORV32_WDT.CTRL` shall be written the upper-most (MSB-aligned) 16 bit of the
write data have to contain the "watchdog access password". If the password is incorrect the write access is entirely ignored
and the watchdog hardware module will **not acknowledge** the bus write access leading to a **store access fault exception**.
Read accesses are not affected by the access password at all.
The watchdog is enabled by setting the control register's `WDT_CTRL_EN_ bit. When this bit is cleared, the internal
timeout counter is reset to zero and no interrupt and no system reset can be triggered.
* Watchdog access password (`write_data[31:16]`) = **`0xCA36`**
The internal 32-bit timeout counter is clocked at 1/4096th of the processor's main clock (f~WDT~[Hz] = f~main~[Hz] / 4096).
Whenever this counter reaches the programmed timeout value (_WDT_CTRL_TIMEOUT_ bits in the control register) a
hardware reset is triggered. In order to inform the application of an imminent timeout, an optional CPU interrupt is
triggered when the timeout counter reaches **half** of the programmed timeout value.
The watchdog is "fed" by writing `1` to the _WDT_CTRL_RESET_ control register bit, which
will reset the internal timeout counter back to zero.
**Timeout Configuration**
The watchdog is enabled by setting the control register's `WDT_CTRL_EN_ bit. The clock used to increment the
internal counter is selected via the 3-bit _WDT_CTRL_CLK_SELx_ prescaler:
[cols="^3,^3,>4"]
[options="header",grid="rows"]
|=======================
| **`WDT_CTRL_CLK_SELx`** | Main clock prescaler | Timeout period in clock cycles
| `0b000` | 2 | 2 097 152
| `0b001` | 4 | 4 194 304
| `0b010` | 8 | 8 388 608
| `0b011` | 64 | 67 108 864
| `0b100` | 128 | 134 217 728
| `0b101` | 1024 | 1 073 741 824
| `0b110` | 2048 | 2 147 483 648
| `0b111` | 4096 | 4 294 967 296
|=======================
The _WDT_CTRL_HALF_ flag of the control register `CTRL` indicates that at least half of the maximum timeout
value has already been reached. The watchdog is "fed" by setting the _WDT_CTRL_RESET_ control register bit, which
will reset the timeout counter.
**Watchdog Action**
Whenever the internal counter overflows the watchdog executes one of two possible actions: either a hard
processor reset is triggered or an interrupt is requested via the CPU's fast interrupt channel #0. The
_WDT_CTRL_MODE_ bit defines the action to be taken on an overflow: when cleared, the watchdog will assert an
IRQ, when set the WDT will cause a system wide reset. The configured action can also be triggered manually at
any time by setting the _WDT_CTRL_FORCE_ bit.
The cause of the last system reset can be determined via the _WDT_CTRL_RCAUSE_ flag. If this flag is
zero, the processor has been reset via the external reset signal (or the on-chip debugger). If this flag is set
the last system reset was caused by the watchdog itself.
[NOTE]
Writing all-zero to the _WDT_CTRL_TIMEOUT_ bits will immediately trigger a system-wide reset.
.Watchdog Interrupt
[NOTE]
A watchdog interrupt can only occur if the watchdog is enabled and interrupt mode is enabled.
A triggered interrupt has to be cleared again by writing zero to the according <<_mip>> CSR bit.
A watchdog interrupt occurs when the watchdog is enabled and the internal counter reaches half of the programmed
timeout value. A triggered interrupt has to be explicitly cleared by writing zero to the according <<_mip>> CSR bit.
.Watchdog Operation during Debugging
[IMPORTANT]
By default the watchdog stops operation when the CPU enters debug mode and will resume normal operation after
the CPU has left debug mode again. This will prevent an unintended watchdog timeout (and a hardware reset if configured)
during a debug session. However, the watchdog can also be configured to keep operating even when the CPU is in debug
mode by setting the control register's _WDT_CTRL_DBEN_ bit.
the CPU has left debug mode again. This will prevent an unintended watchdog timeout during a debug session. However,
the watchdog can also be configured to keep operating even when the CPU is in debug mode by setting the control
register's _WDT_CTRL_DBEN_ bit.
.Watchdog Operation during CPU Sleep Mode
[NOTE]
By default the watchdog keeps operating when the CPU enters sleep mode. However, the watchdog can also be paused while
the CPU is sleeping by setting the _WDT_CTRL_PAUSE_ control register bit.
.Watchdog Operation during CPU Sleep
[IMPORTANT]
By default the watchdog stops operating when the CPU enters sleep mode. However, the watchdog can also be configured
to keep operating even when the CPU is in sleep mode by setting the control register's _WDT_CTRL_SEN_ bit.
**Configuration Lock**
The watchdog control register can be locked to protect the current configuration from being modified. The lock is activated by
setting the _WDT_CTRL_LOCK_ bit. In the locked state any write access to the control register's configuration flags is
ignored (see table below, "writable if locked"). Read accesses to the control register as well as watchdog resets (_WDT_CTRL_RESET_)
and forced watchdog actions (_WDT_CTRL_FORCE_) are not affected.
The watchdog control register can be locked to protect the current configuration from being modified. The lock is
activated by setting the _WDT_CTRL_LOCK_ bit. In the locked state any write access to the control register is entirely
ignored (see table below, "writable if locked"). Read accesses to the control register as well as watchdog resets
(by setting the _WDT_CTRL_RESET_ flag) are not affected.
The lock is removed by a system reset, which can be triggered via the external hardware reset signal, the on-chip debugger
or the watchdog itself (if _WDT_CTRL_MODE_ is set).
The lock bit can only be set if the WDT is already enabled (_WDT_CTRL_EN_ is set).
The lock bit can only be cleared again by a system-wide hardware reset.
**Cause of last Hardware Reset**
The cause of the last system hardware reset can be determined via the _WDT_CTRL_RCAUSE_ flag. If this flag is
zero, the processor has been reset via the external reset signal (or the on-chip debugger). If this flag is set,
the last system reset was caused by the watchdog itself.
**Register Map**
@ -103,18 +82,12 @@ or the watchdog itself (if _WDT_CTRL_MODE_ is set).
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Reset value | Writable if locked | Function
.14+<| `0xffffffbc` .14+<| `NEORV32_WDT.CTRL` <|`0` _WDT_CTRL_EN_ ^| r/w ^| `0` ^| no <| watchdog enable
<|`1` _WDT_CTRL_CLK_SEL0_ ^| r/w ^| `0` ^| no .3+<| 3-bit clock prescaler select
<|`2` _WDT_CTRL_CLK_SEL1_ ^| r/w ^| `0` ^| no
<|`3` _WDT_CTRL_CLK_SEL2_ ^| r/w ^| `0` ^| no
<|`4` _WDT_CTRL_MODE_ ^| r/w ^| `0` ^| no <| overflow action: `1`=reset, `0`=IRQ
<|`5` _WDT_CTRL_RCAUSE_ ^| r/- ^| `0` ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog
<|`6` _WDT_CTRL_RESET_ ^| -/w ^| - ^| yes <| reset watchdog when set, auto-clears
<|`7` _WDT_CTRL_FORCE_ ^| -/w ^| - ^| yes <| force configured watchdog action when set, auto-clears
<|`8` _WDT_CTRL_LOCK_ ^| r/w ^| `0` ^| no <| lock access to configuration when set, clears only on system reset (via external reset signal OR watchdog reset action = reset)
<|`9` _WDT_CTRL_DBEN_ ^| r/w ^| `0` ^| no <| allow WDT to continue operation even when CPU is in debug mode
<|`10` _WDT_CTRL_HALF_ ^| r/- ^| `0` ^| - <| set if at least half of the max. timeout counter value has been reached
<|`11` _WDT_CTRL_PAUSE_ ^| r/w ^| `0` ^| no <| pause WDT when CPU is in sleep mode
<|`15:12` - ^| r/- ^| - ^| - <| _reserved_, reads as zero
<|`31:16` _WDT_CTRL_PWD_ ^| -/w ^| - ^| - <| watchdog write access password, has to be `0xCA36`, reads as zero
.8+<| `0xffffffbc` .8+<| `NEORV32_WDT.CTRL` <|`0` _WDT_CTRL_EN_ ^| r/w ^| `0` ^| no <| watchdog enable
<|`1 _WDT_CTRL_LOCK_ ^| r/w ^| `0` ^| no <| lock configuration when set, clears only on system reset, can only be set if enable bit is set already
<|`2` _WDT_CTRL_DBEN_ ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in debug mode
<|`3` _WDT_CTRL_SEN_ ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in sleep mode
<|`4` _WDT_CTRL_RESET_ ^| -/w ^| - ^| yes <| reset watchdog when set, auto-clears
<|`5` _WDT_CTRL_RCAUSE_ ^| r/- ^| `0` ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog
<|`7:6` - ^| r/- ^| - ^| - <| _reserved_, reads as zero
<|`31:8` _WDT_CTRL_TIMEOUT_MSB_ : _WDT_CTRL_TIMEOUT_LSB_ ^| r/w ^| 0 ^| no <| 24-bit watchdog timeout value
|=======================