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minor edits

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stnolting 2020-06-24 17:12:45 +02:00
parent 624193de00
commit ead0be3645
5 changed files with 10 additions and 12 deletions
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2
rtl/core/neorv32_bootloader_image.vhd
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@ -982,7 +982,7 @@ package neorv32_bootloader_image is
00000971 => x"4c420a0a",
00000972 => x"203a5644",
00000973 => x"206e754a",
00000974 => x"32203332",
00000974 => x"32203432",
00000975 => x"0a303230",
00000976 => x"3a565748",
00000977 => x"00002020",

13
rtl/core/neorv32_cpu_alu.vhd
View file

@ -141,7 +141,7 @@ begin
-- -------------------------------------------------------------------------------------------
-- less than (x < y) --
cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
cmp_opy <= (opc(opc'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
cmp_opy <= (opc(opc'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a less
sub_res <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
@ -177,10 +177,8 @@ begin
shift_cnt <= std_ulogic_vector(unsigned(shift_cnt) - 1);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
shift_sreg <= shift_sreg(shift_sreg'left-1 downto 0) & '0';
elsif (ctrl_i(ctrl_alu_shift_ar_c) = '0') then -- SRL: shift right logical
shift_sreg <= '0' & shift_sreg(shift_sreg'left downto 1);
else -- SRA: shift right arithmetical
shift_sreg <= shift_sreg(shift_sreg'left) & shift_sreg(shift_sreg'left downto 1);
else -- SRL: shift right logical / SRA: shift right arithmetical
shift_sreg <= (shift_sreg(shift_sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shift_sreg(shift_sreg'left downto 1);
end if;
end if;
end if;
@ -194,7 +192,7 @@ begin
shift_run <= '1' when (shift_cnt /= "00000") or (shift_start = '1') else '0';
-- Corprocessor Interface -----------------------------------------------------------------
-- Coprocessor Interface ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
cp_interface: process(rstn_i, clk_i)
begin
@ -229,14 +227,13 @@ begin
-- co-processor operation running? --
cp_run <= cp_busy or cp_start;
--FIXME: insert cp result into alu stream
-- ALU Function Select --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shift_sreg)
begin
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modification)
when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modification only)
when alu_cmd_sub_c => alu_res <= sub_res;
when alu_cmd_add_c => alu_res <= add_res;
when alu_cmd_xor_c => alu_res <= opa xor opb;

2
rtl/core/neorv32_cpu_regfile.vhd
View file

@ -1,7 +1,7 @@
-- #################################################################################################
-- # << NEORV32 - CPU Register File >> #
-- # ********************************************************************************************* #
-- # General purpose data registers. 32 entries for normal mode, 16 entries for embedd mode - when #
-- # General purpose data registers. 32 entries for normal mode, 16 entries for embedded mode when #
-- # RISC-V M extension is enabled. R0 output is hardwired to zero. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #

3
rtl/core/neorv32_package.vhd
View file

@ -149,7 +149,7 @@ package neorv32_package is
constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
constant ctrl_rf_clear_rs1_c : natural := 18; -- force rs1=r0
constant ctrl_rf_clear_rs2_c : natural := 19; -- force r21=r0
constant ctrl_rf_clear_rs2_c : natural := 19; -- force rs2=r0
-- alu --
constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
@ -229,6 +229,7 @@ package neorv32_package is
constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
-- system/csr --
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
-- RISC-V Funct3 --------------------------------------------------------------------------

2
sw/example/hw_analysis/main.c
View file

@ -70,10 +70,10 @@ int main() {
// check if UART unit is implemented at all
if (neorv32_uart_available() == 0) {
return 0; // nope, no UART unit synthesized :(
}
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
}
// capture all exceptions and give debug info via UART